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Architecture Design of Network-on-Chip
in1
in2
in3
in1
in2
in1
D Q
clr
D Q
clr
D Q
clr
out3
out2
out1
En
clk
reset
Figure 3.8
Implementation of priority logic.
When more than one input channel modules send their request signals
to a particular output channel, the SA selects one request signal by following a round-robin strategy for avoiding the starvation problem. It sends
a grant signal (x-gnt) to that request (Figure 3.7). Thus, the input channel
receives the grant (x-gnt) signal and starts passing flits in a pipelined fashion till this x-gnt signal is high. This grant signal is also an input to the
ORS block. The read-ok and data-out signals from the input channel are also
input to the ORS block as shown in Figure 3.7. The ORS block just passes
the selected data and the read-ok signal to the OB depending on the x-gnt
signal. Depending on the out-req signal that represents the availability of
the FIFO buffer of next router’s input channel, rd-en is generated and data
(router-out) comes out from OB synchronously with router-clk. The OFC
block takes the full signal of OB and generates the x-RD signal by inverting it. It also takes the router-out signal and generates the out-val signal by
checking the eop and bop bits.
The implementation of round-robin arbiter is presented in the following text.
The round-robin arbiter is based on priority logic. Figure 3.8 shows a design
of priority logic with three inputs and three outputs. The priority of inputs is
in descending order from in1 to in3. Thus, in1 has the highest priority, in2 has
the next highest priority, and in3 has the lowest priority. The D flip-flop is used
for avoiding glitch due to ANDing. The round-robin arbiter consists of a single
priority logic as shown in Figure 3.9. The input to the priority logic is selected
by a MUX. Here, in1 has the highest priority, in2 has the next highest priority,
and in3 has the lowest priority. The inputs to the MUX are fed in a round-robin
fashion. The output of the priority logic will generate the grant signals (gnt1,
gnt2, gnt3) by using a look-up table (LUT), which is shown in Table 3.1. The
select line of the MUX is generated by using a Moore finite state machine (FSM)
and changes its value only when all the outputs of the priority logic block are
at logic 0. The D flip-flops are used to generate glitch-free grant signals.
The data path of the above wormhole architecture is shown in Figure 3.10.
One IB and one RC are connected to every incoming physical channel, whereas one OB and one SA are connected to every outgoing physical channel.