3
Architecture Design of Network-on-Chip

3.1 Introduction
This chapter focuses on the architectural design of wormhole and virtual channel (VC) routers for NoC. The salient contributions of this chapter are as follows:
1. To support globally asynchronous locally synchronous style of communication, a gray counter-based dual-clock first-in first-out (FIFO)
has been designed and used in NoC router.
2. Design of wormhole router for mesh-of-tree (MoT) topology has
been described in detail.
3. To mitigate the head-of-line (HoL) blocking problem of wormhole
router-based network, VC router has also been implemented.
The rest of the chapter is organized as follows: Section 3.2 describes the
switching technique and packet format of 4  × 4 MoT-based NoC. Sections
3.3 and 3.4 discuss the design of dual-clock FIFO and globally asynchronous
locally synchronous (GALS) style of communication, respectively. Sections
3.5 and 3.6 present a detailed architecture design of wormhole and VC
routers, respectively. Section 3.7 describes an adaptive router architecture.
Finally, Section 3.8 summarizes this chapter.
3.2 Switching Techniques and Packet Format
Both wormhole and VC routers follow the packet switching technique.
Messages are sent in terms of packets, which are further decomposed into
flits (flow control units) in the network interface. A flit is a smaller unit over
which flow control is performed. A packet is composed of header, payload,
and tailer flits. Header flit carries information about the source and destination core addresses, whereas payload and tailer flits contain the actual information. For a 4 × 4 MoT, a flit size of 32 bits has been considered. From the
addressing scheme described in Chapter 2, each core address in a 4 × 4 MoT
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