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Interconnection Networks in Network-on-Chip
Pande, P. P., Grecu, C., Ivanov, A., and Saleh, R. 2003b. High-throughput switch-based
interconnect for future SoCs. Proceedings of the IEEE International Workshop on
System-on-Chip for Real Time Applications, pp. 304–310, Calgary, Alberta, Canada.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Pullini, A., Angiolini, F., Bertozzi, D., and Benini, L. 2005. Fault tolerance overhead
in network-on-chip flow control schemes. Proceedings of the ACM Symposium on
Integrated Circuits and Systems Design, pp. 224–229, Florianópolis, Brazil.
Radulescu, A., Dielissen, J., Pestana, S. G., Gangwal, O. P., Rijpkema, E., Wielage, P.,
and Goossens, K. 2005. An efficient on-chip network interface offering guaranteed services, shared memory abstraction, flexible network programming. IEEE
Transactions on CAD of Integrated Circuits and Systems, vol. 24, no. 1, pp. 4–17.
Schroeder, M. D., Birrell, A. D., Burrows, M., Murray, H., Needham, R. M., Rodeheffer,
T. L. 1991. Autonet: A high speed, self configuring, local area network using
point-to-point links. IEEE Journal on Selected Areas in Communications, vol. 9,
pp. 1318–1335.
Singh, S. P., Bhoj, S., Balasubramanian, D., Nagda, T., Bhatia, D., and Balsara, P.
2007. Network interface for NoC based architectures. International Journal of
Electronics, vol. 94, no. 5, pp. 531–547.
Song, Y. H. and Pinkston, T. M. 2003. A progressive approach to handling messagedependent deadlock in parallel computer systems. IEEE Transactions on Parallel
and Distributed Systems, vol. 14, no. 3, pp. 259–275.
Tamhankar, R. R., Murali, S. and Micheli, G. D. 2005. Performance driven reliable
link design for network on chips. Proceedings of the Asia South Pacific Design
Automation Conference, pp. 749–756, Shanghai, People’s Republic of China.
Tortosa, D. S., Ahonen, T., and Nurmi, J. 2004. Issues in the development of a practical
NoC: The Proteo concept. Integration, the VLSI Journal, vol. 38, no. 1, pp. 95–105.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., et al.
2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE Journal
of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.
Vellanki, P., Banerjee, N., and Chata, K. S. 2004. Quality-of-service and error control
techniques for mesh-based network-on-chip architectures. Integration, the VLSI
Journal, vol. 38, pp. 353–382.
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M.,
Miao, C. C., Brown, J. F., and Agarwal, A. 2007. On-chip interconnection architecture of the TILE processor. IEEE Micro, vol. 27, no. 5, pp. 15–31.
West, D. B. 2002. Introduction to Graph Theory. 2nd Edition. Pearson Education, Upper
Saddle River, NJ.
Zeferino, C. A. and Susin, A. A. 2003. SoCIN: A parametric and scalable network-onchip. Proceedings of the IEEE Symposium on Integrated Circuits and Systems Design,
pp. 169–175, São Paulo, Brazil.
Interconnection Networks in Network-on-Chip
Pande, P. P., Grecu, C., Ivanov, A., and Saleh, R. 2003b. High-throughput switch-based
interconnect for future SoCs. Proceedings of the IEEE International Workshop on
System-on-Chip for Real Time Applications, pp. 304–310, Calgary, Alberta, Canada.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Pullini, A., Angiolini, F., Bertozzi, D., and Benini, L. 2005. Fault tolerance overhead
in network-on-chip flow control schemes. Proceedings of the ACM Symposium on
Integrated Circuits and Systems Design, pp. 224–229, Florianópolis, Brazil.
Radulescu, A., Dielissen, J., Pestana, S. G., Gangwal, O. P., Rijpkema, E., Wielage, P.,
and Goossens, K. 2005. An efficient on-chip network interface offering guaranteed services, shared memory abstraction, flexible network programming. IEEE
Transactions on CAD of Integrated Circuits and Systems, vol. 24, no. 1, pp. 4–17.
Schroeder, M. D., Birrell, A. D., Burrows, M., Murray, H., Needham, R. M., Rodeheffer,
T. L. 1991. Autonet: A high speed, self configuring, local area network using
point-to-point links. IEEE Journal on Selected Areas in Communications, vol. 9,
pp. 1318–1335.
Singh, S. P., Bhoj, S., Balasubramanian, D., Nagda, T., Bhatia, D., and Balsara, P.
2007. Network interface for NoC based architectures. International Journal of
Electronics, vol. 94, no. 5, pp. 531–547.
Song, Y. H. and Pinkston, T. M. 2003. A progressive approach to handling messagedependent deadlock in parallel computer systems. IEEE Transactions on Parallel
and Distributed Systems, vol. 14, no. 3, pp. 259–275.
Tamhankar, R. R., Murali, S. and Micheli, G. D. 2005. Performance driven reliable
link design for network on chips. Proceedings of the Asia South Pacific Design
Automation Conference, pp. 749–756, Shanghai, People’s Republic of China.
Tortosa, D. S., Ahonen, T., and Nurmi, J. 2004. Issues in the development of a practical
NoC: The Proteo concept. Integration, the VLSI Journal, vol. 38, no. 1, pp. 95–105.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., et al.
2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE Journal
of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.
Vellanki, P., Banerjee, N., and Chata, K. S. 2004. Quality-of-service and error control
techniques for mesh-based network-on-chip architectures. Integration, the VLSI
Journal, vol. 38, pp. 353–382.
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M.,
Miao, C. C., Brown, J. F., and Agarwal, A. 2007. On-chip interconnection architecture of the TILE processor. IEEE Micro, vol. 27, no. 5, pp. 15–31.
West, D. B. 2002. Introduction to Graph Theory. 2nd Edition. Pearson Education, Upper
Saddle River, NJ.
Zeferino, C. A. and Susin, A. A. 2003. SoCIN: A parametric and scalable network-onchip. Proceedings of the IEEE Symposium on Integrated Circuits and Systems Design,
pp. 169–175, São Paulo, Brazil.