Index
365
L avg under localized traffic,
110–111, 110f, 111f, 112f
throughput vs. locality factor,
109–110, 110f
having WH router, 93–103
accepted traffic vs. offered load,
97, 97f
energy consumption, 102–103,
102f, 103f
L avg under localized traffic, 99–101,
99t, 100f, 101f
network area estimation, 94–95,
94t, 95t
network aspect ratio, 96–97, 96t
throughput vs. locality factor,
98–99, 98f
Multicast test cost, 244
Multicast wrapper unit (MWU), 240
Multicast mode, 239
data transfer, 240f
transport, 241f
Multilevel voltage scaling (MVS), 160
Multiobjective adaptive immune
algorithm (MAIA), 149
Multiple error-correcting (MEC)
codes, 220
Multiple supply voltage (MSV), 160
Multiprocessor system-on-chip
(MPSoC) architecture, 1,
13, 291
N
Negative-bias temperature instability
(NBTI), 194
Network assignment (NA), 148
Network diameter, 14
Network interface (NI) module, 3, 31,
46–48, 47f, 127
Network layer, 5
Network-on-chip (NoC), 3
3D, 317
4 × 4 optical, 355f
abstraction layers, 4–5
development research issues, 5–8, 7f
application mapping, 7
communication infrastructure, 5
communication paradigm, 6
evaluation framework, 6
evaluation methodologies of, 75–81
cost metrics, 80–81
performance metrics, 78, 80
examples, 8–10
interconnect
bus encoding scheme for, 212f
low-swing signaling in, 172f
mesh-based, 323–324, 324f
paradigm, 4f
photonic, 317–318, 354
reconfigurations for ASIC-based, 290
SoC to, 3–5
testing
with input/output cores for,
245, 245f
issues, 236
wireless, 318, 354–355, 356f
Network processors, 127
Network topologies, 14–29
average distance, 25–29

BFT network, 21, 21f

binary tree network, 19, 20f

CMESH network, 17–18, 18f

EFTI network, 21, 22f

Flattened BFT, 23, 24f

folded torus network, 16, 17f

mesh network, 15f

MoT network, 22, 23f, 26f

number of edges, 25

octagon network, 17, 18f

spidergon network, 19, 19f

SPIN network, 20, 20f

torus network, 15, 16f

NoC links
four node with unidirectional,
243, 244f
low-power methods for, 166–172
bus energy model, 167–168
low-power coding, 168–170
low-swing signaling, 171–172
on-chip serialization, 170–171
testing, 237–238
NoC routers, low-power methods for
clock gating, 158–159, 158f
gate-level power optimization,
159–160

multivoltage design, 160–164

multi-V T design, 164–165

power gating, 165–166