Index
363
Input FIFO buffer (IB), 58
Input flow controller (IFC), 58
Input read switch (IRS), 58
Integer linear programming (ILP), 123
-based approach in local
reconfiguration, 299–301
constraints, 300–301
objective function, 300
parameters and variables,
300, 300t
for flexible router placement
constraints, 279–281
objective function, 279
variables, 278–279
formulation, 123–127
other, 127–128
in testing cores, 250–253
Intellectual property (IP), 119, 235
calculate ranking, 131
sets, 130
merging of, 131, 133f
refreshing, 131
Interconnection network, 13f
Internal power consumption, 156
Iteration (T i ), idle periods in, 83
K
Kernighan–Lin (K–L) partitioning
scheme, 140–141
L
Largest communication first (LCF)
heuristics, 138
Latency, 80; see also Average overall
latency (L avg )
Least common ancestor (LCA)
algorithm, 33, 93, 340
Linear feedback shift register (LFSR),
218, 219f
Link-based mapping (LBMAP), 139
Link reconfiguration
estimating channel bandwidth
utilization, 311–312
modified router architecture,
312, 312f
Link utilization, 174, 181–182, 182f
Locality factor, 85
MoT with WH router
energy consumption at different,
88–90, 88f, 89f
L avg at different, 86–87, 87f
throughput vs., 85–86, 87f
throughput vs.
in 3D NoC with self-similar
traffic, 341–342, 341t
MoT with VC router,
109–110, 110f
MoT with WH router, 98–99, 98f
Local link, 76
Local reconfiguration approach,
291–304, 292f, 293f
area overhead, 294–296
of different architectures, 297t
for module types, 295, 295t
parameters for Orion, 294, 295t
router areas, 295, 295t
design flow, 296–299, 298f
configuration generation, 299
construction of CCG, 298
mapping of CCG, 299
ILP-based approach

constraints, 300–301

objective function, 300

parameters and variables,
300, 300t
iterative reconfiguration, 303–304
multiplexers, 293–294
PSO formulation, 301–302
routers, 292–293
selection logic, 294, 294f
Look-up table (LUT), 61, 62f
Low-power code (LPC), 168–170, 221
Low-power methods for NoC links,
166–172
bus energy model, 167–168
low-power coding, 168–170
low-swing signaling, 171–172, 172f
on-chip serialization, 170–171, 171f
Low-power methods for NoC routers
clock gating, 158–159
router-level, 159f
write clock of FIFO, 158, 158f
gate-level power optimization,
159–160, 160f