333
Three-Dimensional Integration of Network-on-Chip
≈20 μm
≈ 5 m m
≈10 mm
Figure 11.8
A 3D 2 × 2 × 4 Mesh-2 network.
the length and breadth of the chip, respectively. Hence, the links need to be
pipelined to restrict its delay within the clock cycle budget. In a 3D environment, when the same BFT network is mapped onto a four-layer 3D IC, the
longest interswitch wire length is reduced by a factor of 4, approximately.
This reduced wire length leads to the reduction in the number of pipelining
stages and also reduces the link energy consumption. As the interlayer distance is very less, there is no need to pipeline the interlayer links. Hence, the
root router (shown as dotted node in Figure 11.9) is bypassed.
A probable distribution of cores, routers, and links of the proposed MoTbased 3D NoC with two cores attached to each leaf level router is shown
in Figure 11.10. This network also has three types of routers: (1) leaf having