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Three-Dimensional Integration of Network-on-Chip
11.3.2 Performance and Cost evaluation
For evaluating the performance of 3D NoC, a SystemC-based cycle-accurate
simulator has been developed as described in Chapter 4. In this work, similar
to Chapter 4, each core is inserted in a tile of dimension 2.5 mm × 2.5 mm. Due
to increased burden of placing multilayer IPs in a limited number of layers, as
depicted in the work of Feero and Pande (2009), this work assumes each core
to be placed in a single silicon layer. A thorough evaluation of performance
of 3D MoT structure along with its energy consumption and area overhead is
performed. The results are compared with 3D BFT and 3D mesh-based networks having the same number of cores. Here, performance and cost of all
the networks are compared for a 32-core-based system. For a fair comparison
with 3D MoT having two cores at each leaf level router, another variation of 3D
mesh topology, connecting two cores to each router, is also included in this
comparative study. To reduce the number of interlayer vias and to simplify
the floorplanning problem, unlike ciliated 3D mesh structure, two cores are
placed in a single layer. In this work, it has been considered that single link
traversal of length approximately 2.5 mm can be completed in a single clock
cycle. The length of the core-to-router link is taken to be 1.25 mm. Similar to
Chapter 4, Figures 11.7 through 11.10 show the possible distributions of cores,
routers, and links for chip area estimation. These diagrams enable us to compare the area overheads of alternate NoC topologies under consideration.
In general, in 3D mesh structure having a single core attached with each
router, the middle layers have three types of routers: (1) center having node
degree 7, (2) edge having node degree 6, and (3) corner having node degree
5. For a mesh structure with 32 cores, a probable distribution of cores, routers, and links of a 2 × 4 × 4 network is shown in Figure 11.7 with bisection
width 8. Depending on the connectivity, the middle layer of this network
has two types of routers: (1) edge having node degree 6 and (2) corner having
node degree 5. The length of the links between the two rows and the last two
columns in each layer is taken as tens of micron, whereas the rest of the
inter-router links in a single layer is 2.5 mm long, as shown in Figure 11.7.
The length of the vertical links between two adjacent layers is taken to be
20 μm, as in the work of Feero and Pande (2009).
In the second variant of mesh network, having two cores connected with
each router, the middle layer consists of three types of routers: (1) center having node degree 8, (2) edge having node degree 7, and (3) corner having node
degree 6. For a 32-core-based system, a similar distribution of cores, routers,
and links of such 2 × 2 × 4 mesh architecture is shown in Figure 11.8. The
middle layer of this network has only one type of router with node degree 6.
The number of routers required and the bisection width of this network are
half of those for the first variant of 3D mesh network. As wire delay increases
exponentially with its length, the links having more than 2.5 mm length are
pipelined. The registers used for pipelining are shown as small white nodes
in Figure  11.8. In this structure, the links between two adjacent rows in a