315
Reconfigurable Network-on-Chip Design
Modarressi, M. and Sarbazi-Azad, H. 2007. Power-aware mapping for reconfigurable NoC architectures. International Conference on Computer Design, IEEE,
pp. 417–422.
Modarressi, M., Sarbazi-Azad, H., and Tavakkol, A. 2010. An efficient dynamically
reconfigurable on-chip network architecture. ACM/IEEE Design Automation
Conference, IEEE, pp. 166–169.
Modarressi, M., Tavakkol, A., and Sarbazi-Azad, H. 2011. Application-aware topology reconfiguration for on-chip networks. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 19, pp. 2010–2022.
Rana, V., Atienza, D., Santambrogio, M.D., Sciuto, D., and Micheli, G. De. 2009.
A reconfigurable network-on-chip architecture for optimal multi-processor SoC
communication, VLSI-SOC, IEEE, pp. 1–20.
Soumya, J., Sharma, A., and Chattopadhyay, S. 2013. Multi-application network-onchip design using global mapping and local reconfiguration. ACM Transactions
on Reconfigurable Technologies and Systems, vol. 7, no. 2, p. 2014.
Stensgaard, M. B. and Sparso, J. 2008. ReNoC: A network-on-chip architecture
with reconfigurable topology. The 2nd ACM/IEEE International Symposium on
Networks-on-Chip, IEEE, pp. 55–64.
Wu, L. W., Tang, W. X., and Hsu, Y. 2011. A novel architecture and routing algorithm
for dynamic reconfigurable network-on-chip. International Symposium on Parallel
and Distributed Processing with Applications, IEEE, pp. 177–182.
Zheng, L., Jueping, C., Ming, D., Lei, Y., and Zan, L. 2010. Hybrid communication
reconfigurable network on chip for MPSoC. International Conference on Advanced
Information Networking and Applications, IEEE, pp. 356–361.
Reconfigurable Network-on-Chip Design
Modarressi, M. and Sarbazi-Azad, H. 2007. Power-aware mapping for reconfigurable NoC architectures. International Conference on Computer Design, IEEE,
pp. 417–422.
Modarressi, M., Sarbazi-Azad, H., and Tavakkol, A. 2010. An efficient dynamically
reconfigurable on-chip network architecture. ACM/IEEE Design Automation
Conference, IEEE, pp. 166–169.
Modarressi, M., Tavakkol, A., and Sarbazi-Azad, H. 2011. Application-aware topology reconfiguration for on-chip networks. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 19, pp. 2010–2022.
Rana, V., Atienza, D., Santambrogio, M.D., Sciuto, D., and Micheli, G. De. 2009.
A reconfigurable network-on-chip architecture for optimal multi-processor SoC
communication, VLSI-SOC, IEEE, pp. 1–20.
Soumya, J., Sharma, A., and Chattopadhyay, S. 2013. Multi-application network-onchip design using global mapping and local reconfiguration. ACM Transactions
on Reconfigurable Technologies and Systems, vol. 7, no. 2, p. 2014.
Stensgaard, M. B. and Sparso, J. 2008. ReNoC: A network-on-chip architecture
with reconfigurable topology. The 2nd ACM/IEEE International Symposium on
Networks-on-Chip, IEEE, pp. 55–64.
Wu, L. W., Tang, W. X., and Hsu, Y. 2011. A novel architecture and routing algorithm
for dynamic reconfigurable network-on-chip. International Symposium on Parallel
and Distributed Processing with Applications, IEEE, pp. 177–182.
Zheng, L., Jueping, C., Ming, D., Lei, Y., and Zan, L. 2010. Hybrid communication
reconfigurable network on chip for MPSoC. International Conference on Advanced
Information Networking and Applications, IEEE, pp. 356–361.
