314
Network-on-Chip
strategies attempt to relocate cores to the neighboring routers of the one to
which it was originally mapped. These strategies provide the advantages of
shorter link lengths. However, topology reconfiguration-based approaches
may create long links. Suitable arrangement needs to be done to take care of
the link delays. The link reconfiguration-based approaches can change the
link directions between routers to cater to heavy traffic flow in one direction,
whereas in the other direction traffic may be negligible. However, the strategy needs good amount of modification to the router architecture.
References
Ahmad, B., Erdogan, A. T., and Khawam, S. 2006. Architecture of a dynamically
reconfigurable NoC for adaptive reconfigurable MPSoC. NASA/ESA Conference
on Adaptive Hardware and Systems, IEEE, pp. 405–411.
Atienza, D., Angiolini, F., Murali, S., Pullini, A., Benini, L., and De Micheli G. 2008.
Network-on-chip design and synthesis outlook, Integration—The VLSI Journal,
vol. 41, no. 3, pp. 340–359.
Avakian, A., Nafziger, J., Panda, A., and Vemuri, R. 2010. A reconfigurable architecture for multicore systems. IEEE International Symposium on Parallel & Distributed
Processing, IEEE, pp. 1–8.
Bartic, T. A., Mignolet, J. Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., and
Lauwereins, R. 2003. Highly scalable network-on-chip for reconfigurable systems. International Symposium on System-on-Chip, IEEE, pp. 79–82.
Bartic, T. A., Mignolet, J. Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S.,
and Lauwereins, R. 2005. Topology adaptive network-on-chip design and
implementation. IEE Proceedings Computers and Digital Techniques, vol. 152, no. 4,
pp. 467–472.
Dally, W. J. and Towles, B. 2001. Route packets, not wires: On-chip interconnection
networks, Design Automation Conference, IEEE, pp. 684–689.
Ding, H., Gu, H., Li, B., and Du, K. 2012. Configuring algorithm for reconfigurable
network-on-chip architecture. International Conference on Consumer Electronics,
Communications and Networks, IEEE, pp. 222–225.
Dumitriu, V. and Khan, G. N. 2009. Throughput-oriented NoC topology generation
and analysis for high performance SoCs, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 17, no. 10, pp. 1433–1446.
Elmiligi, H., El-Kharashi, M. W., and Gebali, F. 2007. Introducing OperaNP: A reconfigurable NoC-based platform. Canadian Conference on Electrical and Computer
Engineering, IEEE, pp. 940–943.
Kunert, K., Wecksten, M., and Jonsson, M. 2007. Algorithm for the choice of topology in reconfigurable on-chip networks with real time support. International
Conference on Nano-Networks, ACM.
Lan, Y. C., Lin, H. A., Lo, S. H., Hu, Y. H., and Chen, S. J. 2011. A bidirectional NoC
(BiNoC) architecture with dynamic self-reconfigurable channel. IEEE Transactions
on Computer Aided Design of Integrated Circuits and Systems, IEEE, pp. 427–440.
Network-on-Chip
strategies attempt to relocate cores to the neighboring routers of the one to
which it was originally mapped. These strategies provide the advantages of
shorter link lengths. However, topology reconfiguration-based approaches
may create long links. Suitable arrangement needs to be done to take care of
the link delays. The link reconfiguration-based approaches can change the
link directions between routers to cater to heavy traffic flow in one direction,
whereas in the other direction traffic may be negligible. However, the strategy needs good amount of modification to the router architecture.
References
Ahmad, B., Erdogan, A. T., and Khawam, S. 2006. Architecture of a dynamically
reconfigurable NoC for adaptive reconfigurable MPSoC. NASA/ESA Conference
on Adaptive Hardware and Systems, IEEE, pp. 405–411.
Atienza, D., Angiolini, F., Murali, S., Pullini, A., Benini, L., and De Micheli G. 2008.
Network-on-chip design and synthesis outlook, Integration—The VLSI Journal,
vol. 41, no. 3, pp. 340–359.
Avakian, A., Nafziger, J., Panda, A., and Vemuri, R. 2010. A reconfigurable architecture for multicore systems. IEEE International Symposium on Parallel & Distributed
Processing, IEEE, pp. 1–8.
Bartic, T. A., Mignolet, J. Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., and
Lauwereins, R. 2003. Highly scalable network-on-chip for reconfigurable systems. International Symposium on System-on-Chip, IEEE, pp. 79–82.
Bartic, T. A., Mignolet, J. Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S.,
and Lauwereins, R. 2005. Topology adaptive network-on-chip design and
implementation. IEE Proceedings Computers and Digital Techniques, vol. 152, no. 4,
pp. 467–472.
Dally, W. J. and Towles, B. 2001. Route packets, not wires: On-chip interconnection
networks, Design Automation Conference, IEEE, pp. 684–689.
Ding, H., Gu, H., Li, B., and Du, K. 2012. Configuring algorithm for reconfigurable
network-on-chip architecture. International Conference on Consumer Electronics,
Communications and Networks, IEEE, pp. 222–225.
Dumitriu, V. and Khan, G. N. 2009. Throughput-oriented NoC topology generation
and analysis for high performance SoCs, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 17, no. 10, pp. 1433–1446.
Elmiligi, H., El-Kharashi, M. W., and Gebali, F. 2007. Introducing OperaNP: A reconfigurable NoC-based platform. Canadian Conference on Electrical and Computer
Engineering, IEEE, pp. 940–943.
Kunert, K., Wecksten, M., and Jonsson, M. 2007. Algorithm for the choice of topology in reconfigurable on-chip networks with real time support. International
Conference on Nano-Networks, ACM.
Lan, Y. C., Lin, H. A., Lo, S. H., Hu, Y. H., and Chen, S. J. 2011. A bidirectional NoC
(BiNoC) architecture with dynamic self-reconfigurable channel. IEEE Transactions
on Computer Aided Design of Integrated Circuits and Systems, IEEE, pp. 427–440.