Link
Link
Port 1
Router
Port 2
Port 3
Port 4
Port 5
Topology switch
Link
Link
IP core
307
Reconfigurable Network-on-Chip Design
Figure 10.8
A multiplexer-based implementation.
the NoC clock frequency, as flits may not be able to cross a long link within
a single router clock. For solving these problems, long links are segmented
into fixed-length links connected by a register (one-flit buffer). Data may be
sent over such a link in a pipelined fashion.
10.4.2.1 Application Mapping
The overall mapping problem for this architecture can be stated as follows:
Given a set of input applications using a specific set of IP cores,
1. Attach the cores to different routers in the architecture.
2. Determine the customized topology for each application, based on
mapping and application traffic characteristic.
Link
Port 1
Router
Port 2
Port 3
Port 4
Port 5
Topology switch
Link
Link
IP core
307
Reconfigurable Network-on-Chip Design
Figure 10.8
A multiplexer-based implementation.
the NoC clock frequency, as flits may not be able to cross a long link within
a single router clock. For solving these problems, long links are segmented
into fixed-length links connected by a register (one-flit buffer). Data may be
sent over such a link in a pipelined fashion.
10.4.2.1 Application Mapping
The overall mapping problem for this architecture can be stated as follows:
Given a set of input applications using a specific set of IP cores,
1. Attach the cores to different routers in the architecture.
2. Determine the customized topology for each application, based on
mapping and application traffic characteristic.