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Reconfigurable Network-on-Chip Design
presented in Zheng et al. (2010) which dynamically reconfigures MultiProcessor System-on-Chip (MPSoC) architecture based on bus traffic.
They have used a designable framework that enables topology reconfiguration upon some regular physical network topologies. It provides a customized domain-specific framework for on-chip interconnection, which
applies both NoC-based and bus-based systems to fulfil specific application requirements. A runtime ReNoC framework has been presented in
Rana et al. (2009) based on the partial dynamic reconfiguration capabilities
of FPGAs. This framework dynamically creates or deletes express lines
between SoC components (implementing dynamically circuit-switching
channels) and performs runtime NoC topology and routing table reconfigurations to handle interconnection congestion. A flexible network
design has been presented in Bartic et al. (2003, 2005) which is scalable
and can be changed to accommodate various needs of applications. This
design is realized as part of the platform for reconfigurable systems. It
is suitable for building networks with irregular topologies. An architecture of dynamically reconfigurable NoC has been proposed by Ahmad
et al. (2006) for MPSoC. It dynamically configures itself with respect to
routing, switching, and data packet size with the change in communication requirements of the system at runtime. This work generates specific
topology for the application running on NoC, which is a time-consuming
and complex approach, as this consists of generating floorplan, network
component placement, and deadlock free routing. Ding et al. (2012) has
proposed a configuration algorithm based on a ReNoC by clustering the
cores. Many cores are connected per router that may lead to increase in
the complexity and power consumption of the routers. Only one application is taken at a time for mapping onto the reconfigured NoC. Dumitriu
and Khan (2009) has presented an approach for throughput oriented NoC
generation technique.
10.3 Local Reconfiguration Approach
In this section, a locally reconfigurable NoC architecture is presented
(Soumya et al. 2013). The architecture is built around the one reported in the
work of Ding et al. (2012) (shown in Figure 10.1).
Compared to many other reconfiguration topologies (Stensgaard et al.
2008; Modarressi et al. 2011) that attempt to reduce distances between communicating cores via the introduction of configurable switches, this architecture uses multiplexers. The cores have limited choice to get attached to the
routers; however, the overall architecture remains a mesh with small regular interconnects, bounded delay, and the applicability of standard mesh
routing algorithms for the resulting application’s message communication.