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Testing of Network-on-Chip Architectures
Cota, E., Carro, L., and Lubaszewski, M. 2004. Reusing an on-chip network for the
test of core-based systems. ACM Transactions on Design Automation of Electronic
Systems, vol. 9, no. 4, pp. 471–499.
Cota, E. and Liu, C. 2006. Constraint driven test scheduling for NoC based systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 25, no. 11, pp. 2465–2478.
Cuivello, M., Dey, S., Bai, X., and Zhao, Y. 1999. Fault modeling and simulation for
crosstalk in system-on-chip inerconnects. IEEE/ACM International Conference on
Computer Aided Design, IEEE, pp. 297–303.
Farah, R. and Harmanani, H. 2010. A method for efficient NoC test scheduling using
deterministic routing. IEEE International SOC Conference, IEEE, pp. 363–366.
Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the Theory
of NP-Completeness. W. H. Freeman and Co., San Francisco, CA.
Grecu, C., Ivanov, A., Saleh, R., and Pande, P. 2007. Testing network-on-chip communication fabrics. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. 26, no. 12, pp. 2201–2214.
Iyengar, V. and Chakrabarty, K., 2002. Test wrapper and test access mechanism
co-optimization for system-on-chip. Journal of Electronic Testing: Theory and
Applications, vol. 18, pp. 213–230.
Liu, C., Iyengar, V., and Pradhan, D. K. 2006. Thermal-aware testing of network-onchip using multiple frequency clocking. 24th IEEE VLSI Test Symposium. IEEE.
Liu, C., Iyengar, V., Shi, J., and Cota, E. 2005a. Power aware test scheduling in networkon-chip using variable rate on-chip clocking. IEEE VLSI Test Symposium. IEEE.
Liu, C., Veeraraghavan, K., and Iyengar, V. 2005b. Thermal-aware test scheduling
and hot spot temperature minimization for core based systems. 20th IEEE
International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE.
Marinissen, E. J., Goel, S. K., and Lousberg, M. 2000. Wrapper design for embedded
core test. International Test Conference, IEEE, pp. 911–920.
Marinissen, E. J., Kapur, R., Lousberg, M., McLaurin, T., Ricchetti, M., and Zorian, Y.
2002. On IEEE P1500’s standard for embedded core test. Journal of Electronic
Testing: Theory and Applications, vol. 18, pp. 365–383.
Pande, P., Grecu, C., Ivanov, A., Saleh, R., and Micheli, G De. 2005. Design, synthesis,
and test of networks on chip. IEEE Design and Test of Computers, vol. 22, no. 5,
pp. 404–413.
Salamy, H. and Harmanani, H. M. 2011. An optimal formulation for test scheduling network-on-chip using multiple clock rates. IEEE Canadian Conference on
Electrical and Computer Engineering. IEEE.
Testing of Network-on-Chip Architectures
Cota, E., Carro, L., and Lubaszewski, M. 2004. Reusing an on-chip network for the
test of core-based systems. ACM Transactions on Design Automation of Electronic
Systems, vol. 9, no. 4, pp. 471–499.
Cota, E. and Liu, C. 2006. Constraint driven test scheduling for NoC based systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 25, no. 11, pp. 2465–2478.
Cuivello, M., Dey, S., Bai, X., and Zhao, Y. 1999. Fault modeling and simulation for
crosstalk in system-on-chip inerconnects. IEEE/ACM International Conference on
Computer Aided Design, IEEE, pp. 297–303.
Farah, R. and Harmanani, H. 2010. A method for efficient NoC test scheduling using
deterministic routing. IEEE International SOC Conference, IEEE, pp. 363–366.
Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the Theory
of NP-Completeness. W. H. Freeman and Co., San Francisco, CA.
Grecu, C., Ivanov, A., Saleh, R., and Pande, P. 2007. Testing network-on-chip communication fabrics. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. 26, no. 12, pp. 2201–2214.
Iyengar, V. and Chakrabarty, K., 2002. Test wrapper and test access mechanism
co-optimization for system-on-chip. Journal of Electronic Testing: Theory and
Applications, vol. 18, pp. 213–230.
Liu, C., Iyengar, V., and Pradhan, D. K. 2006. Thermal-aware testing of network-onchip using multiple frequency clocking. 24th IEEE VLSI Test Symposium. IEEE.
Liu, C., Iyengar, V., Shi, J., and Cota, E. 2005a. Power aware test scheduling in networkon-chip using variable rate on-chip clocking. IEEE VLSI Test Symposium. IEEE.
Liu, C., Veeraraghavan, K., and Iyengar, V. 2005b. Thermal-aware test scheduling
and hot spot temperature minimization for core based systems. 20th IEEE
International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE.
Marinissen, E. J., Goel, S. K., and Lousberg, M. 2000. Wrapper design for embedded
core test. International Test Conference, IEEE, pp. 911–920.
Marinissen, E. J., Kapur, R., Lousberg, M., McLaurin, T., Ricchetti, M., and Zorian, Y.
2002. On IEEE P1500’s standard for embedded core test. Journal of Electronic
Testing: Theory and Applications, vol. 18, pp. 365–383.
Pande, P., Grecu, C., Ivanov, A., Saleh, R., and Micheli, G De. 2005. Design, synthesis,
and test of networks on chip. IEEE Design and Test of Computers, vol. 22, no. 5,
pp. 404–413.
Salamy, H. and Harmanani, H. M. 2011. An optimal formulation for test scheduling network-on-chip using multiple clock rates. IEEE Canadian Conference on
Electrical and Computer Engineering. IEEE.