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Network-on-Chip
Swap sequence: A swap sequence SS is made up of one or more swap
operators. Swap operation in the swap sequence is applied to a particle for creating new particle. For example, let the swap sequence
SS = {SO 5,6 , SO 2,4 } be applied upon the particle P = {0, 4, 3, 6, 2, 1, 5, 7}.
It creates new particle P New = {0, 4, 3, 6, 2, 5, 1, 7}. To align a particle P k
lbest
with its local best, the swap sequence is identified. Let this be SS k .
Then another swap sequence is identified to align the particle with
lbest
the global best. Let this be SS i
gbest . Now the swap sequence SS k is
applied on particle P k with probability α. Let the modified particle
be P k
lbest . Then the swap sequence SS i
gbest is applied on P k
lbest with probability β. This creates new particle P New . Its fitness is evaluated and
the local best is updated for kth particle, if it is the better than the
previous local best for the particle. If the best fitness in a generation
is better than the global best of the previous generation, the global
best is also updated.
8.4 Summary
Testing NoC is one of the most important and intricate problems to be
solved in NoC-based SoC design. Since the entire chip is being integrated,
it is not possible to assume the correctness of individual components (as
in a board-based design). Both the communication infrastructure and the
cores need to be tested. The infrastructure test includes testing the routers
and links of the NoC. The problem involves having different fault models and test mechanisms for these components. The problem is NP-hard.
However, testing of cores require proper scheduling of the test sessions.
Different variants of the problem have been solved—preemptive versus
nonpreemptive, BIST versus external test, power aware (Liu et al. 2005a),
thermal aware (Liu et al. 2005b, 2006), and so on. A number of test scheduling mechanisms have been reported, such as ILP, heuristics, and metasearch techniques. Overall, a number of dedicated approaches may need
to be combined to get reasonably good reduction in test time and cost.
References
Ahn, J. H. and Kang, S. 2006. Test scheduling of NoC based SoCs using multiple test
clocks. ETRI Journal, vol. 28, no. 4, pp. 475–485.
Bushnell, M. L. and Agrawal, V. D. 2005. Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits. Springer-Verlag, Boston, MA.