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Testing of Network-on-Chip Architectures
area are likely to possess more defects than smaller cores. Hence, it may be
more desirable to test the larger cores first. Thus, the core order part needs to
be reconsidered while formulating the NoC test scheduling algorithm.
Another important constraint is that of peak power consumption during
test. The chip will have a predefined safety level of power dissipation. The
scheduling algorithm must ensure that this power limit is not violated at any
time during test. The total power consumed during testing of a core has two
main components: the power consumed by the core and the power consumed
by the network in transporting the test packets for the core. The power consumed by the core depends on various factors, such as the core design, the test
vectors, and the order of test vectors, which are mostly determined by the core
vendor providing the test patterns. For the purpose of scheduling, the power
consumed by individual cores can be assumed to be available. The power consumed by the wrapper can also be taken along with the core, since the wrapper
is active only when the core is being tested. However, the power consumed by
the network to transport each test packet (P packet ) can be expressed as follows:
P packet = nb routers × P router + nb channels × P channel
where:
nb routers is the number of routers in the path established in the network for
the packet
nb channels is the number of channels in the path
P router is the power consumed by a single router per cycle
P channel is the power consumed by a single channel per cycle
The router power consumption depends on the supply voltage (V dd ), the load
capacitance (C L ), the frequency of operation ( f), the number of flip-flops (nb ff ),
the number of logic gates (nb gt ), and their corresponding expected switching
activities (σ ff ) and (σ gt ), respectively.
P
= C ×V
2
f [( σ + 1 × nb + σ × nb ]
router
L
dd × × ff )
ff
gt
gt
The channel power consumption is given by the following expression. Here,
the load capacitance of the channel is given by the product of number of
wires in the channel (ch w ), the length of the channel (ch l ), and the width of the
wire (wire w ). σ w is the switching factor of the wire.
P channel = V dd × × σ w ×(ch l × wire w × ch w
2
f
)
Since power consumption is calculated per cycle, packet length is not that
significant.
Based on the above constraints and power consumption metric, Cota and
Liu (2006) proposed an improved test scheduling algorithm for cores in NoC.
The cores may be BISTed and have multiple test sessions with individual
Testing of Network-on-Chip Architectures
area are likely to possess more defects than smaller cores. Hence, it may be
more desirable to test the larger cores first. Thus, the core order part needs to
be reconsidered while formulating the NoC test scheduling algorithm.
Another important constraint is that of peak power consumption during
test. The chip will have a predefined safety level of power dissipation. The
scheduling algorithm must ensure that this power limit is not violated at any
time during test. The total power consumed during testing of a core has two
main components: the power consumed by the core and the power consumed
by the network in transporting the test packets for the core. The power consumed by the core depends on various factors, such as the core design, the test
vectors, and the order of test vectors, which are mostly determined by the core
vendor providing the test patterns. For the purpose of scheduling, the power
consumed by individual cores can be assumed to be available. The power consumed by the wrapper can also be taken along with the core, since the wrapper
is active only when the core is being tested. However, the power consumed by
the network to transport each test packet (P packet ) can be expressed as follows:
P packet = nb routers × P router + nb channels × P channel
where:
nb routers is the number of routers in the path established in the network for
the packet
nb channels is the number of channels in the path
P router is the power consumed by a single router per cycle
P channel is the power consumed by a single channel per cycle
The router power consumption depends on the supply voltage (V dd ), the load
capacitance (C L ), the frequency of operation ( f), the number of flip-flops (nb ff ),
the number of logic gates (nb gt ), and their corresponding expected switching
activities (σ ff ) and (σ gt ), respectively.
P
= C ×V
2
f [( σ + 1 × nb + σ × nb ]
router
L
dd × × ff )
ff
gt
gt
The channel power consumption is given by the following expression. Here,
the load capacitance of the channel is given by the product of number of
wires in the channel (ch w ), the length of the channel (ch l ), and the width of the
wire (wire w ). σ w is the switching factor of the wire.
P channel = V dd × × σ w ×(ch l × wire w × ch w
2
f
)
Since power consumption is calculated per cycle, packet length is not that
significant.
Based on the above constraints and power consumption metric, Cota and
Liu (2006) proposed an improved test scheduling algorithm for cores in NoC.
The cores may be BISTed and have multiple test sessions with individual