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Network-on-Chip
Algorithm NoC_Schedule
1. Start with sorted cores in decreasing order of test time;
2. Permute all possible order of I/O pairs;
3. For specified number of permutations of I/O pairs do
4.
While there are unscheduled cores do
5.
For each unscheduled core do
6.
Find a free I/O pair;
7.
If no free I/O pair then
8.
Update current time; Repeat from 4;
9.
Else
10.
Check the corresponding routing path;
11.
If path is blocked
12.
If all cores have been attempted
13.
Update current time; Repeat from 4;
14.
Else
15.
Try next core in the list;
16.
Else
17.
Assign core to the path; Update time
labels;
18.
Repeat from 3 for a user-defined number of core permutations;
The nonpreemptive test scheduling algorithm discussed so far lacks flexibility,
in the sense that the minimum manageable unit in test scheduling is the full test
application time of a core. For example, the power consumption of a core during
test is generally much higher than that during normal mode of operation. This
happens as the successive functional inputs are generally correlated, while in
order to maximize fault coverage, the successive test patterns in a test sequence
are highly uncorrelated. This excessive power dissipation and lack of heat transfer can create hot spots within the chip. Applying the entire test suite continually can increase the temperature significantly. Hence, it may be necessary to
split the test into multiple sessions and put idle times in between for cooling.
In a nonpreemptive test, the test resources are held by the core currently being
tested, this causes wastage of test time and resource utilization. A preemptive
test can overcome this situation by performing tests in a preemptive fashion.
Many a times, for testing complex cores, multiple test sets are used. For
example, a core may be tested by both built-in self-test (BIST) and external test
sessions. The tests may also need to be partially ordered. The BIST being onchip may be applied at a much higher frequency than the external testing.
The BIST is applied first, as it can detect the random-detectable faults (the
faults that can be detected by random patterns) easily. For the remaining random pattern-resistant faults, the test patterns generated by dedicated algorithms are applied through the external tester. Testing of memory cores may
be carried out earlier than the logic cores. Once tested, the memory cores can
be used to test the logic cores. Larger cores occupying more amount of chip
Network-on-Chip
Algorithm NoC_Schedule
1. Start with sorted cores in decreasing order of test time;
2. Permute all possible order of I/O pairs;
3. For specified number of permutations of I/O pairs do
4.
While there are unscheduled cores do
5.
For each unscheduled core do
6.
Find a free I/O pair;
7.
If no free I/O pair then
8.
Update current time; Repeat from 4;
9.
Else
10.
Check the corresponding routing path;
11.
If path is blocked
12.
If all cores have been attempted
13.
Update current time; Repeat from 4;
14.
Else
15.
Try next core in the list;
16.
Else
17.
Assign core to the path; Update time
labels;
18.
Repeat from 3 for a user-defined number of core permutations;
The nonpreemptive test scheduling algorithm discussed so far lacks flexibility,
in the sense that the minimum manageable unit in test scheduling is the full test
application time of a core. For example, the power consumption of a core during
test is generally much higher than that during normal mode of operation. This
happens as the successive functional inputs are generally correlated, while in
order to maximize fault coverage, the successive test patterns in a test sequence
are highly uncorrelated. This excessive power dissipation and lack of heat transfer can create hot spots within the chip. Applying the entire test suite continually can increase the temperature significantly. Hence, it may be necessary to
split the test into multiple sessions and put idle times in between for cooling.
In a nonpreemptive test, the test resources are held by the core currently being
tested, this causes wastage of test time and resource utilization. A preemptive
test can overcome this situation by performing tests in a preemptive fashion.
Many a times, for testing complex cores, multiple test sets are used. For
example, a core may be tested by both built-in self-test (BIST) and external test
sessions. The tests may also need to be partially ordered. The BIST being onchip may be applied at a much higher frequency than the external testing.
The BIST is applied first, as it can detect the random-detectable faults (the
faults that can be detected by random patterns) easily. For the remaining random pattern-resistant faults, the test patterns generated by dedicated algorithms are applied through the external tester. Testing of memory cores may
be carried out earlier than the logic cores. Once tested, the memory cores can
be used to test the logic cores. Larger cores occupying more amount of chip