250
Network-on-Chip
Thus, the total time required for testing is given by
h src→core + (l − 1) + 1 + [1 + Max{h src→core + (l − 1) , h core→sink + (l − 1)}] ] × (p − 1)
+ h c ore→sink + (l − 1) = [1 + Max{h src→core , h core→sink } + (l − 1 1)]
× p + [Min{h src→core , h core→sink } + (l − 1)]
Test scheduling problem can be formulated as follows:
Given a NoC with n cores having their test parameters (number of test
patterns, scan chain length, etc.) and k number of I/O pairs, determine an
assignment of cores to I/O pairs and the time schedule to minimize the
overall test time of all the cores present in the NoC.
There are a few variants of the problem reported in the literature. A multifrequency test scheduling assumes that in test mode, individual cores can
be made to operate at different frequencies, thus requiring proportional test
times. Some formulations put a limit on the total peak power that can be
sustained by the chip, whereas some other formulations are concerned about
minimizing the peak temperature of the NoC or making the temperature
uniform in the chip. The solution strategies proposed can broadly be divided
into the following categories:
1. Exact solution via mathematical tools, such as integer linear programming (ILP)
2. Heuristic algorithms
3. Evolutionary algorithms, such as particle swarm optimization (PSO)
8.3.2 iLP Formulation
ILP formulation of an optimization problem can provide its exact solution
at the cost of execution time of the solver. For the problem of core testing in
NoC, Salamy and Harmanani (2011) reported an ILP formulation. The overall problem addressed is as follows:
Given a system of N c cores, N p input/output ports, and a set of clock rates
F c (at which individual cores may operate during testing), map the cores
to the input/output ports and obtain a test schedule so that the overall
test time is minimized.
To start with, a few definitions are noted. T iuc = Test time of core i on input/
output pair u under clock frequency c, 1 ≤ i ≤ N c ,
1 ≤ p ≤ N p and c ∈ F c
S i = Start time of core i
I ix = Input/output pair of core i, 1 ≤ x ≤ N p
Network-on-Chip
Thus, the total time required for testing is given by
h src→core + (l − 1) + 1 + [1 + Max{h src→core + (l − 1) , h core→sink + (l − 1)}] ] × (p − 1)
+ h c ore→sink + (l − 1) = [1 + Max{h src→core , h core→sink } + (l − 1 1)]
× p + [Min{h src→core , h core→sink } + (l − 1)]
Test scheduling problem can be formulated as follows:
Given a NoC with n cores having their test parameters (number of test
patterns, scan chain length, etc.) and k number of I/O pairs, determine an
assignment of cores to I/O pairs and the time schedule to minimize the
overall test time of all the cores present in the NoC.
There are a few variants of the problem reported in the literature. A multifrequency test scheduling assumes that in test mode, individual cores can
be made to operate at different frequencies, thus requiring proportional test
times. Some formulations put a limit on the total peak power that can be
sustained by the chip, whereas some other formulations are concerned about
minimizing the peak temperature of the NoC or making the temperature
uniform in the chip. The solution strategies proposed can broadly be divided
into the following categories:
1. Exact solution via mathematical tools, such as integer linear programming (ILP)
2. Heuristic algorithms
3. Evolutionary algorithms, such as particle swarm optimization (PSO)
8.3.2 iLP Formulation
ILP formulation of an optimization problem can provide its exact solution
at the cost of execution time of the solver. For the problem of core testing in
NoC, Salamy and Harmanani (2011) reported an ILP formulation. The overall problem addressed is as follows:
Given a system of N c cores, N p input/output ports, and a set of clock rates
F c (at which individual cores may operate during testing), map the cores
to the input/output ports and obtain a test schedule so that the overall
test time is minimized.
To start with, a few definitions are noted. T iuc = Test time of core i on input/
output pair u under clock frequency c, 1 ≤ i ≤ N c ,
1 ≤ p ≤ N p and c ∈ F c
S i = Start time of core i
I ix = Input/output pair of core i, 1 ≤ x ≤ N p