6
Network-on-Chip
and routers are allowed to operate at their own clocks, giving rise to a GALS
scheme. Another important hardware aspect in designing a complete NoC
is the integration of cores with the routers. This needs the design of NI modules between the two.
The second dimension of research deals with the communication paradigm
on a given NoC platform. Once the infrastructure has been finalized, the next
important task is to design the communication methodology between the
cores via the established network. Routing policies, switching techniques,
congestion control, power and thermal management, and fault tolerance
and reliability issues are the main focus of this set. It, first of all, necessitates the fixing of routing strategy. This is one of the very rich areas of
research in NoC design. It has profound effect on the performance of the
NoC as this chiefly determines the number of hops to be traversed in each
communication, congestion, traffic load distribution in different routers,
and so on. The domain is often complicated by the requirement to support
the quality-of-service (QoS). Arbitration of network resources in terms of
FIFOs and channels between the contending simultaneous communications is essential to ensure freedom from problems such as livelock and
deadlock. Like off-chip communications, on-chip communications also suffer from capacitive crosstalk and electromagnetic radiations, corrupting the
data being transmitted. This makes it essential to adopt some fault-tolerant
schemes in the communication. As all designs are now invariably power
aware, the same is the requirement for NoC as well. It is required to judge
very critically the voltages and frequencies at which individual cores and
routers are made to operate to satisfy the overall performance requirement
with a minimum power budget.
The third dimension of research is paying attention to the design of an
evaluation framework for NoC by applying stochastic and application-specific
traffic. As the MPSoCs contain a large number of cores connected in some
topology via routers and interconnection links, it is mandatory to have a
clear idea about their performance before any investment is made in manufacturing the systems. The potential faults and drawbacks, if any, must be
identified at the design phase to avoid huge loss after getting the silicon
chips. Though many theoretical studies exist that can predict the behavior of
such a system, they are mostly for congestion-free environment and under
the assumption that all cores are equally active in producing traffic load to
the network. Both of these assumptions are highly optimistic for any practical design of moderate size. This necessitates the design of high-quality
NoC simulators to produce a behavior similar to that of the actual NoC. The
simulator should model the network at the granularity of individual hardware blocks and wires in terms of functionality, delay, power, and so on.
In the absence of the actual traffic pattern for applications, often synthetic
traffic is used. This synthetic traffic should mimic the behavior of the actual
core that it corresponds to. With confidence gained after determining the
throughput, latency, and bandwidth of the network through simulation,
Network-on-Chip
and routers are allowed to operate at their own clocks, giving rise to a GALS
scheme. Another important hardware aspect in designing a complete NoC
is the integration of cores with the routers. This needs the design of NI modules between the two.
The second dimension of research deals with the communication paradigm
on a given NoC platform. Once the infrastructure has been finalized, the next
important task is to design the communication methodology between the
cores via the established network. Routing policies, switching techniques,
congestion control, power and thermal management, and fault tolerance
and reliability issues are the main focus of this set. It, first of all, necessitates the fixing of routing strategy. This is one of the very rich areas of
research in NoC design. It has profound effect on the performance of the
NoC as this chiefly determines the number of hops to be traversed in each
communication, congestion, traffic load distribution in different routers,
and so on. The domain is often complicated by the requirement to support
the quality-of-service (QoS). Arbitration of network resources in terms of
FIFOs and channels between the contending simultaneous communications is essential to ensure freedom from problems such as livelock and
deadlock. Like off-chip communications, on-chip communications also suffer from capacitive crosstalk and electromagnetic radiations, corrupting the
data being transmitted. This makes it essential to adopt some fault-tolerant
schemes in the communication. As all designs are now invariably power
aware, the same is the requirement for NoC as well. It is required to judge
very critically the voltages and frequencies at which individual cores and
routers are made to operate to satisfy the overall performance requirement
with a minimum power budget.
The third dimension of research is paying attention to the design of an
evaluation framework for NoC by applying stochastic and application-specific
traffic. As the MPSoCs contain a large number of cores connected in some
topology via routers and interconnection links, it is mandatory to have a
clear idea about their performance before any investment is made in manufacturing the systems. The potential faults and drawbacks, if any, must be
identified at the design phase to avoid huge loss after getting the silicon
chips. Though many theoretical studies exist that can predict the behavior of
such a system, they are mostly for congestion-free environment and under
the assumption that all cores are equally active in producing traffic load to
the network. Both of these assumptions are highly optimistic for any practical design of moderate size. This necessitates the design of high-quality
NoC simulators to produce a behavior similar to that of the actual NoC. The
simulator should model the network at the granularity of individual hardware blocks and wires in terms of functionality, delay, power, and so on.
In the absence of the actual traffic pattern for applications, often synthetic
traffic is used. This synthetic traffic should mimic the behavior of the actual
core that it corresponds to. With confidence gained after determining the
throughput, latency, and bandwidth of the network through simulation,