Core
Core
Core
Core
Encoder
Encoder
Decoder
Decoder
Decoder
Sender
NI
Receiver
NI
Sender
NI
Receiver
NI
Switch A
Switch A
Switch B
Switch B
Queuing buffers
Packet buffers
Credit signal
(a)
Credit signal
Data
ack
TMR
TMR
TMR
Packet buffers
Valid
TMR
No data
Circular

(queuing and retransmission buffers)

(b)
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Signal Integrity and Reliability of Network-on-Chip
detection and retransmission. Error detection and retransmission can be
either end to end or switch to switch (Murali et al. 2005).
In the end-to-end error detection scheme, a parity bit or cyclic redundancy
check (CRC) bit is added to the packet. The parity or CRC encoder is added
to the sender network interface (NI) and the decoder is added to the receiver
NI. The error detection mechanism is performed only at the receiver NI. The
receiver NI sends a nonacknowledgment (NACK) or acknowledgment (ACK)
signal (labeled as credit signal in Figure 7.19a) back to the sender, depending
on whether the data contained an error or not. The sender will retransmit the
packet if an error is detected at the receiver NI. But if the error corrupts the
header flit, which contains the information of destination address, the packet
will perhaps not reach the destination. Therefore, the header flit is protected by
parity or CRC codes, which the switch checks at each hop traversal. If a switch
detects an error on a packet’s header flit, it drops the packet. To account for
errors on the ACK or NACK signals, a time-out mechanism is incorporated
for retransmission at the sender. The overall scheme is shown in Figure 7.19a.
Figure 7.19
Retransmission scheme: (a) End to end; (b) switch to switch.