u(t)
clock 4×
Counter
Register
current
add (+)
Left shift
Right shift
D
Register
previous
SUB
U L (n)
clock Tc
(a)
ψ L (n)
U L (n)
ψ L (n − 1)
(b)
182
Network-on-Chip
Direct estimation can be realized with a counter, reducing the complexity
of the estimator and additional hardware overhead caused by the DFS link
controller. A counter at each output port gathers the total number of cycles that
are used to pass a flit in each control period by counting u(t) with 4 times of
the clock frequency for accurate measurement (Figure 6.17a). Function u(t) is
assigned to the write enable signal of the router, and the counter value is sampled in each control period to complete the measurement of the link utilization.
History-based link estimator uses exponential weighted average utilization to combine the current [U L (n ) ] and the past [Ψ L (n − 1)] link utilization
history, smoothing and predicting future link utilization Ψ L ( n) as follows:
Weight × U L ( n) + Ψ L (n − 1)
Ψ L (n) =
(6.13)
Weight + 1
where:
Ψ ( 0) = ψ , i ∈ N
L
0
Weight is the contribution factor of current link utilization level to the history-based link estimator
The hardware overhead is an important factor for the design of the estimator.
Soteriou and Peh (2004) realized the history-based estimator with two shifters and an adder by setting weight equal to 3 and reducing additional hardware overhead caused by the prediction mechanism. Figure 6.17b shows the
hardware circuit for the exponential weighted average. The result of direct
estimator is fed to the exponential weighted average calculator to predict the
link utilization. The history-based estimator is a cascade of direct link utilization estimators and an exponential average calculator.
Figure 6.17
History-based link utilization estimator: (a) direct link utilization estimator; (b) exponential
weighted average calculator.
clock 4×
Counter
Register
current
add (+)
Left shift
Right shift
D
Register
previous
SUB
U L (n)
clock Tc
(a)
ψ L (n)
U L (n)
ψ L (n − 1)
(b)
182
Network-on-Chip
Direct estimation can be realized with a counter, reducing the complexity
of the estimator and additional hardware overhead caused by the DFS link
controller. A counter at each output port gathers the total number of cycles that
are used to pass a flit in each control period by counting u(t) with 4 times of
the clock frequency for accurate measurement (Figure 6.17a). Function u(t) is
assigned to the write enable signal of the router, and the counter value is sampled in each control period to complete the measurement of the link utilization.
History-based link estimator uses exponential weighted average utilization to combine the current [U L (n ) ] and the past [Ψ L (n − 1)] link utilization
history, smoothing and predicting future link utilization Ψ L ( n) as follows:
Weight × U L ( n) + Ψ L (n − 1)
Ψ L (n) =
(6.13)
Weight + 1
where:
Ψ ( 0) = ψ , i ∈ N
L
0
Weight is the contribution factor of current link utilization level to the history-based link estimator
The hardware overhead is an important factor for the design of the estimator.
Soteriou and Peh (2004) realized the history-based estimator with two shifters and an adder by setting weight equal to 3 and reducing additional hardware overhead caused by the prediction mechanism. Figure 6.17b shows the
hardware circuit for the exponential weighted average. The result of direct
estimator is fed to the exponential weighted average calculator to predict the
link utilization. The history-based estimator is a cascade of direct link utilization estimators and an exponential average calculator.
Figure 6.17
History-based link utilization estimator: (a) direct link utilization estimator; (b) exponential
weighted average calculator.