152
Network-on-Chip
Jang, W. and Pan, D. Z. 2010. A3MAP: Architecture-aware analytic mapping for
network-on-chip. Asia and South Pacific Design Automation Conference, IEEE
Press, pp. 523–528.
Janidarmian, M., Khademzadeh, A., Fekr, A. R., and Bokharaei, V. S. 2010. Citrine:
A methedology for application-specific network-on-chips design. Proceedings of
World Congress on Engineering and Computer Science, vol. 1, Springer, pp. 196–202.
Janidarmian, M., Khademzadeh, A., and Tavanpour, M. 2009. Onyx: A new heuristic bandwidth-constrained mapping of cores onto network on chip. IEICE
Electronics Express, vol. 6, no. 1, pp. 1–7.
Jena, R. K. and Sharma, G. K. 2007. A multi-objective evolutionary algorithm based
optimization model for network-on-chip. IEEE International Conference on
Information Technology, IEEE Press, pp. 977–982.
Kennedy, I. and Eberhart, R. C. 1995. Particle swarm optimization. Proceedings of IEEE
International Conference on Neural Networks, New Jersey, IEEE Press, pp. 1942–1948.
Koziris, N., Romesis, M., Tsanakas, P., and Papakonstantinou, G. 2000. An efficient
algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures. Proceedings of 8th Euro PDP, IEEE Press, pp. 406–413.
Lei, T. and Kumar, S. 2003. A two-step genetic algorithm for mapping task graphs to
a network on chip architecture. Proceedings of the Euromicro Symposium on Digital
System Design (DSD), IEEE Press, pp. 180–187.
Lei, W. and Xiang, L. 2010. Energy- and latency-aware NoC mapping based on discrete particle swarm optimization. Proceedings of IEEE International Conference on
Communications and Mobile Computing, IEEE Press, pp. 263–268.
Lu, Z., Xia, L., and Jantsch, A. 2008. Cluster-based simulated annealing for mapping
cores onto 2D mesh networks on chip. Proceedings of Design and Diagnostics of
Electronic Circuits and Systems, IEEE Press, pp. 1–6.
Majeti, D., Pasalapudi, A., and Yalamanchili, K. 2009. Low energy tree based network
on chip architectures using homogeneous routers for bandwidth and latency
constrained multimedia applications. International Conference on Emerging Trends
in Engineering and Technology, IEEE Press, pp. 358–363.
Marcon, C., Borin, A., Susin, A., Carro, L., and Wagner, F. 2005a. Time and energy efficient mapping of embeded applications onto NoCs. Proceedings of Asia and South
Pacific Design Automation Conference, IEEE Press, vol. 1, pp. 33–38.
Marcon, C., Calazans, N., Moraes, F., Susin, A., Reis, I., and Hessel, F. 2005b. Exploring
NoC mapping strategies: An energy and timing aware technique. Proceedings of
Design, Automation and Test in Europe Conference and Exhibition, IEEE Press, vol. 1,
pp. 502–507.
Marcon, C., Moreno, E. I., Calazans, N. L. V., and Moraes, F. G. 2008. Comparison of
network-on-chip mapping algorithms targeting low energy consumption. IET
Computer & Digital Technique, vol. 2, no. 6, pp. 471–482.
Mehran, R., Saeidi, S., Khademzadeh, A., and Kusha, A. A. 2007. Spiral: A heuristic
mapping algorithm for network on chip. IEICE Electronics Express, vol. 4, no. 15,
pp. 478–484.
Murali, S., Benini, L., and Micheli, G. De. 2005. Mapping and physical planning of
networks-on-chip architectures with quality-of-service guarantees. Asia and
South Pacific Design Automation Conference, IEEE Press, pp. 27–32.
Murali, S. and Micheli, G. De. 2004a. Bandwidth constrained mapping of cores onto
NoC architectures. Proceedings of Design, Automation and Test in Europe Conference
and Exhibition, IEEE Press, vol. 2, pp. 896–901.
Network-on-Chip
Jang, W. and Pan, D. Z. 2010. A3MAP: Architecture-aware analytic mapping for
network-on-chip. Asia and South Pacific Design Automation Conference, IEEE
Press, pp. 523–528.
Janidarmian, M., Khademzadeh, A., Fekr, A. R., and Bokharaei, V. S. 2010. Citrine:
A methedology for application-specific network-on-chips design. Proceedings of
World Congress on Engineering and Computer Science, vol. 1, Springer, pp. 196–202.
Janidarmian, M., Khademzadeh, A., and Tavanpour, M. 2009. Onyx: A new heuristic bandwidth-constrained mapping of cores onto network on chip. IEICE
Electronics Express, vol. 6, no. 1, pp. 1–7.
Jena, R. K. and Sharma, G. K. 2007. A multi-objective evolutionary algorithm based
optimization model for network-on-chip. IEEE International Conference on
Information Technology, IEEE Press, pp. 977–982.
Kennedy, I. and Eberhart, R. C. 1995. Particle swarm optimization. Proceedings of IEEE
International Conference on Neural Networks, New Jersey, IEEE Press, pp. 1942–1948.
Koziris, N., Romesis, M., Tsanakas, P., and Papakonstantinou, G. 2000. An efficient
algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures. Proceedings of 8th Euro PDP, IEEE Press, pp. 406–413.
Lei, T. and Kumar, S. 2003. A two-step genetic algorithm for mapping task graphs to
a network on chip architecture. Proceedings of the Euromicro Symposium on Digital
System Design (DSD), IEEE Press, pp. 180–187.
Lei, W. and Xiang, L. 2010. Energy- and latency-aware NoC mapping based on discrete particle swarm optimization. Proceedings of IEEE International Conference on
Communications and Mobile Computing, IEEE Press, pp. 263–268.
Lu, Z., Xia, L., and Jantsch, A. 2008. Cluster-based simulated annealing for mapping
cores onto 2D mesh networks on chip. Proceedings of Design and Diagnostics of
Electronic Circuits and Systems, IEEE Press, pp. 1–6.
Majeti, D., Pasalapudi, A., and Yalamanchili, K. 2009. Low energy tree based network
on chip architectures using homogeneous routers for bandwidth and latency
constrained multimedia applications. International Conference on Emerging Trends
in Engineering and Technology, IEEE Press, pp. 358–363.
Marcon, C., Borin, A., Susin, A., Carro, L., and Wagner, F. 2005a. Time and energy efficient mapping of embeded applications onto NoCs. Proceedings of Asia and South
Pacific Design Automation Conference, IEEE Press, vol. 1, pp. 33–38.
Marcon, C., Calazans, N., Moraes, F., Susin, A., Reis, I., and Hessel, F. 2005b. Exploring
NoC mapping strategies: An energy and timing aware technique. Proceedings of
Design, Automation and Test in Europe Conference and Exhibition, IEEE Press, vol. 1,
pp. 502–507.
Marcon, C., Moreno, E. I., Calazans, N. L. V., and Moraes, F. G. 2008. Comparison of
network-on-chip mapping algorithms targeting low energy consumption. IET
Computer & Digital Technique, vol. 2, no. 6, pp. 471–482.
Mehran, R., Saeidi, S., Khademzadeh, A., and Kusha, A. A. 2007. Spiral: A heuristic
mapping algorithm for network on chip. IEICE Electronics Express, vol. 4, no. 15,
pp. 478–484.
Murali, S., Benini, L., and Micheli, G. De. 2005. Mapping and physical planning of
networks-on-chip architectures with quality-of-service guarantees. Asia and
South Pacific Design Automation Conference, IEEE Press, pp. 27–32.
Murali, S. and Micheli, G. De. 2004a. Bandwidth constrained mapping of cores onto
NoC architectures. Proceedings of Design, Automation and Test in Europe Conference
and Exhibition, IEEE Press, vol. 2, pp. 896–901.