151
Application Mapping on Network-on-Chip
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2010. Energy aware design methedologies for application specific NoC. Proceedings of NORCHIP, IEEE Press, pp. 1–4.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2011. GA based congestion aware
topology generation for application specific NoC. IEEE International Symposium
on Electronics Design, Test, and Application, IEEE Press, pp. 93–98.
Darbari, F. M., Khademzadeh, A., and Fard, G. G. 2009a. Evaluating the performance
of a chaos genetic algorithm for solving the network on chip mapping problem.
International Conference on Computational Science and Engineering, IEEE Press,
pp. 366–373.
Darbari, F. M., Khademzadeh, A., and Fard, G. G. 2009b. CGMAP: A new approach
to network-on-chip mapping problem. IEICE Electronics Express, vol. 6, no. 1,
pp. 27–34.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2008a. Power-aware
topology optimization for network-on-chips. IEEE International Symposium on
Circuits and Systems, IEEE Press, pp. 360–363.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2008b. Applicationspecific networks-on-chip topology customization using network partitioning.
1st International Forum on Next-generation Multicore/manycore Technologies. ACM.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2009. Power optimization for application-specific networks-on-chips: A topology-based approach.
Journal of Microprocessor and Microsystems, vol. 33, pp. 343–355.
Fard, G. G., Khademzadeh, A., and Darbari, F. M. 2009. Evaluating the performance
of one-dimensional chaotic maps in network-on-chip mapping problem. IEICE
Electronics Express, vol. 6, no. 12, pp. 811–817.
Fekr, A. R., Khademzadeh, A., Janidarmian, M., and Bokharaei, V. S. 2010. Bandwidth/
fault/contention aware application-specific NoC using PSO as a mapping generator. Proceedings of the World Congress on Engineering, IAENG, vol. 1, pp. 247–252.
Fen, G. and Ning, W. 2010. Genetic algorithm based mapping and routing approach for
network on chip architectures. Chinese Journal of Electronics, vol. 19, no. 1, pp. 91–96.
Ghosh, P., Sen, A. Sen, and Hall, A. 2009. Energy efficient application mapping to NoC
processing elements operating at multiple voltage levels. IEEE International
Symposiun on Network-on-Chip, IEEE Press, pp. 80–85.
Guilan, L., Hai, Z., and Chunhe, S. 2008. Convergence analysis of a dynamic discrete
PSO algorithm. International Conference on Intelligent Networks and Intelligent
Systems, IEEE Press, pp. 89–92.
Hansson, A., Goossens, K., and Radulescu, A. 2005. A unified approach to constrained mapping and routing on network-on-chip architectures. IEEE/ACM
International Conference on Hardware/Software Codesign and System Synthesis, IEEE
Press, pp. 75–80.
Harmanani, H. M. and Farah, R. 2008. A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area. IEEE International
Workshop on Circuits and Systems and TAISA Conference, IEEE Press, pp. 29–32.
Hu, J. and Marculescu, R. 2005. Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, vol. 24, no. 4, pp. 551–562.
Huang, J., Buckl, C., Raabe, A., and Knool, A. 2011. Energy-aware task allocation
for network-on-chip based heterogeneous multiprocessor systems. Euromicro
International Conference on Parallel, Distributed and Network based Processing, IEEE
Press, pp. 447–454.
Application Mapping on Network-on-Chip
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2010. Energy aware design methedologies for application specific NoC. Proceedings of NORCHIP, IEEE Press, pp. 1–4.
Choudhary, N., Gaur, M. S., Laxmi, V., and Singh, V. 2011. GA based congestion aware
topology generation for application specific NoC. IEEE International Symposium
on Electronics Design, Test, and Application, IEEE Press, pp. 93–98.
Darbari, F. M., Khademzadeh, A., and Fard, G. G. 2009a. Evaluating the performance
of a chaos genetic algorithm for solving the network on chip mapping problem.
International Conference on Computational Science and Engineering, IEEE Press,
pp. 366–373.
Darbari, F. M., Khademzadeh, A., and Fard, G. G. 2009b. CGMAP: A new approach
to network-on-chip mapping problem. IEICE Electronics Express, vol. 6, no. 1,
pp. 27–34.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2008a. Power-aware
topology optimization for network-on-chips. IEEE International Symposium on
Circuits and Systems, IEEE Press, pp. 360–363.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2008b. Applicationspecific networks-on-chip topology customization using network partitioning.
1st International Forum on Next-generation Multicore/manycore Technologies. ACM.
Elmiligi, H., Morgan, A. A., Kharashi, M. W. E., and Gebali, F. 2009. Power optimization for application-specific networks-on-chips: A topology-based approach.
Journal of Microprocessor and Microsystems, vol. 33, pp. 343–355.
Fard, G. G., Khademzadeh, A., and Darbari, F. M. 2009. Evaluating the performance
of one-dimensional chaotic maps in network-on-chip mapping problem. IEICE
Electronics Express, vol. 6, no. 12, pp. 811–817.
Fekr, A. R., Khademzadeh, A., Janidarmian, M., and Bokharaei, V. S. 2010. Bandwidth/
fault/contention aware application-specific NoC using PSO as a mapping generator. Proceedings of the World Congress on Engineering, IAENG, vol. 1, pp. 247–252.
Fen, G. and Ning, W. 2010. Genetic algorithm based mapping and routing approach for
network on chip architectures. Chinese Journal of Electronics, vol. 19, no. 1, pp. 91–96.
Ghosh, P., Sen, A. Sen, and Hall, A. 2009. Energy efficient application mapping to NoC
processing elements operating at multiple voltage levels. IEEE International
Symposiun on Network-on-Chip, IEEE Press, pp. 80–85.
Guilan, L., Hai, Z., and Chunhe, S. 2008. Convergence analysis of a dynamic discrete
PSO algorithm. International Conference on Intelligent Networks and Intelligent
Systems, IEEE Press, pp. 89–92.
Hansson, A., Goossens, K., and Radulescu, A. 2005. A unified approach to constrained mapping and routing on network-on-chip architectures. IEEE/ACM
International Conference on Hardware/Software Codesign and System Synthesis, IEEE
Press, pp. 75–80.
Harmanani, H. M. and Farah, R. 2008. A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area. IEEE International
Workshop on Circuits and Systems and TAISA Conference, IEEE Press, pp. 29–32.
Hu, J. and Marculescu, R. 2005. Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, vol. 24, no. 4, pp. 551–562.
Huang, J., Buckl, C., Raabe, A., and Knool, A. 2011. Energy-aware task allocation
for network-on-chip based heterogeneous multiprocessor systems. Euromicro
International Conference on Parallel, Distributed and Network based Processing, IEEE
Press, pp. 447–454.