127
Application Mapping on Network-on-Chip
Solving this optimization problem can produce a solution to the mapping
problem.
5.3.1 Other iLP Formulations
A mixed ILP (MILP)-based task mapping for heterogeneous multiprocessor
systems is reported in the work of Bender (1996). In this heterogeneous multiprocessor, some processors are programmable, whereas others are application specific. The model determines the optimization trade-off between
the execution time, the processor (general-purpose or application-specific
processor), and the communication cost. This is a hardware/software codesign process that runs iteratively until the design goal is met. An MILP formulation for mapping cores onto NoC while considering the choice of core
placements, switches for each core, and network interfaces (NIs) for communication has been proposed by Rhee et al. (2004). It is reported that the energy
consumption is much less compared to other mapping techniques for some
real, as well as, random benchmarks. An integrated approach for mapping
of cores onto heterogeneous processor/memory-based NoC topologies and
physical planning has been presented by Murali et al. (2005), where the position and size of the cores and network components are computed. For initial
mapping, they followed a greedy mapping of cores onto the specified topology, and then in the improvement phase, the relative core positions are fixed
by Tabu search. An MILP-based physical planning algorithm has been formulated to improve the area and power of the final design and also to guarantee the quality of service (QoS) for the application. Srinivasan et al. (2006)
presented an MILP formulation for synthesis of custom NoC architectures.
Here the optimization objective is to minimize the power consumption, subject to the performance constraints. In case of linear programming (LP), the
main bottleneck is runtime. To reduce runtime, they partitioned the application task graph into a number of clusters. The MILP formulation for topology design is then utilized and partial solutions are generated. At the end,
the final mapped custom topology is generated by adding physical links
between the ports of neighboring routers of the clusters.
The network processors incorporate features such as symmetric multiprocessing (SMP), block multithreading, and multiple memory elements to support high-performance networking applications. Mapping an application
onto a complex multiprocessor, multithreaded network processor is a difficult task. Ostler and Chatha (2007) presented a two-stage ILP formulation
for process allocation and data mapping on SMP and block multithreadingbased network processor. They compared the normalized results from their
models, such as without optimizations, multithreading-aware data mapping,
process transformation, and multithreading-aware data mapping with process transformation. Power/energy control is a very important issue in case
of NoC-based chip multiprocessors (CMPs). Ozturk et al. (2007) attempted
to minimize the energy by shutting down certain communication links in
Application Mapping on Network-on-Chip
Solving this optimization problem can produce a solution to the mapping
problem.
5.3.1 Other iLP Formulations
A mixed ILP (MILP)-based task mapping for heterogeneous multiprocessor
systems is reported in the work of Bender (1996). In this heterogeneous multiprocessor, some processors are programmable, whereas others are application specific. The model determines the optimization trade-off between
the execution time, the processor (general-purpose or application-specific
processor), and the communication cost. This is a hardware/software codesign process that runs iteratively until the design goal is met. An MILP formulation for mapping cores onto NoC while considering the choice of core
placements, switches for each core, and network interfaces (NIs) for communication has been proposed by Rhee et al. (2004). It is reported that the energy
consumption is much less compared to other mapping techniques for some
real, as well as, random benchmarks. An integrated approach for mapping
of cores onto heterogeneous processor/memory-based NoC topologies and
physical planning has been presented by Murali et al. (2005), where the position and size of the cores and network components are computed. For initial
mapping, they followed a greedy mapping of cores onto the specified topology, and then in the improvement phase, the relative core positions are fixed
by Tabu search. An MILP-based physical planning algorithm has been formulated to improve the area and power of the final design and also to guarantee the quality of service (QoS) for the application. Srinivasan et al. (2006)
presented an MILP formulation for synthesis of custom NoC architectures.
Here the optimization objective is to minimize the power consumption, subject to the performance constraints. In case of linear programming (LP), the
main bottleneck is runtime. To reduce runtime, they partitioned the application task graph into a number of clusters. The MILP formulation for topology design is then utilized and partial solutions are generated. At the end,
the final mapped custom topology is generated by adding physical links
between the ports of neighboring routers of the clusters.
The network processors incorporate features such as symmetric multiprocessing (SMP), block multithreading, and multiple memory elements to support high-performance networking applications. Mapping an application
onto a complex multiprocessor, multithreaded network processor is a difficult task. Ostler and Chatha (2007) presented a two-stage ILP formulation
for process allocation and data mapping on SMP and block multithreadingbased network processor. They compared the normalized results from their
models, such as without optimizations, multithreading-aware data mapping,
process transformation, and multithreading-aware data mapping with process transformation. Power/energy control is a very important issue in case
of NoC-based chip multiprocessors (CMPs). Ozturk et al. (2007) attempted
to minimize the energy by shutting down certain communication links in