460
Compact Models for Integrated Circuit Design
* in the sub-circuit
** Sub-circuit will therefore, over-ride ‘tox, dxl, dxw, dvth,
* cj, cjsw, cjswn, cgo, cgl’ in this LIB.
** g[np]sigma is always 0 when using fixed corners
.param gnmean = 1
.param gpmean = 1
.param gnsigma = 0
.param gpsigma = 0
*
*device: pull down
.param
+toxn_pd_svt = 1.6412E-09
dxln_pd_svt = 1.2E-09
+dxwn_pd_svt = -2.70E-09
dvthn_pd_svt = 1.6768E-02
+cjn_pd_svt = 0.003260
cjswn_pd_svt = 1.070E-14
+cjswgn_pd_svt = 3.2878e-010 cgon_pd_svt = 9.114e-12
+cgln_pd_svt = 3.7665e-011
*
*device: pull down
.param
+toxp_pu_svt = 1.6399E-09
dxlp_pu_svt = 1.2E-09
+dxwp_pu_svt = -2.70E-09
dvthp_pu_svt = -1.8080E-02
+cjp_pu_svt = 0.003603
cjswp_pu_svt = 1.070E-14
+cjswgp_pu_svt = 3.3206e-010 cgop_pu_svt = 9.7696E-13
+cglp_pu_svt = 5.0086E-11
*
*device: pass gate
.param
+toxn_pg_svt = 1.6412E-09
dxln_pg_svt = 1.2E-09
+dxwn_pg_svt = -2.70E-09
dvthn_pg_svt = 1.6768E-02
+cjn_pg_svt = 0.003260
cjswn_pg_svt = 1.070E-14
+cjswgn_pg_svt = 3.2878e-010 cgon_pg_svt = 9.114e-12
+cgln_pg_svt = 3.7665e-011
*
.LIB ‘sram127hp.l’ SUBCKTS_SVT
.ENDL SS_svt
************* Library of FNFP Corner Case with RDD **************
.LIB FF_svt
.param sdvtncorn = -1
.param sdvtpcorn = -1
** Need these defined since the parameters created for MC are
* in the sub-circuit
** Sub-circuit will therefore, over-ride ‘tox, dxl, dxw, dvth,