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Compact Models for Integrated Circuit Design
2. Sample SRAM Compact Model of an Advanced CMOS Technology
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* Example2: 20-nm CMOS technology node SRAM Hspice model library
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* Version:
sram127hp.l *** January 20, 2015 ***
* MODEL:
BSIM4 ( V4.5)
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* Model Information
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* This Rev0 version of sample SPICE model is based on
two-dimensional
* numerical device simulation
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.LIB INTERNAL
*----------------------------------------------------------------------------------------* History of model updates
*----------------------------------------------------------------------------------------* Jan 20, 2015: model created from TCAD-based model
*
: bit cell127: wxn_pd = 76.5; wxn_pg = 63.9;
wxp_pu = 50.4; * L = 35.1 (nm)
*----------------------------------------------------------------------------------------.ENDL INTERNAL
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* Begin header
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* Usage:
*
* Hspice Version: 2007.03, 2008.03, 2009.03
*
* .lib ‘sram127hp.l’ TT
* .lib ‘sram127hp.l’ FF
* .lib ‘sram127hp.l’ SS
* .lib ‘sram127hp.l’ SF
* .lib ‘sram127hp.l’ FS
* .lib ‘sram127hp.l’ MC
*
* .options scale=1
*
* Transistor sub-circuits
* p4_pu_svt : PMOS PULL UP Ldrawn = 0.0351um,
* Wdrawn = 0.0504u
*
x0 d g s b
*
+p4_pu_svt w = w l = l
$$ REQUIRED
*
*--------------------------- optional -----------------------------*
+ z=z
$$ default = 0.1n: s/d length from
* channel
*
+ ad=ad as=as pd=pd ps=ps
$$ default = function of w, l, z
*
+ n_fingers=#fingers
$$ default=1