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Compact Models for Integrated Circuit Design
roll-off [9], and carrier transit time [10]. Due to its simple yet physical model
formulation, SGP model was the most popular BJT model until mid-1990s.
With the continued scaling of modern transistors, some second-order
effects that are not considered by SGP model, such as substrate network, selfheating effects, and avalanche effects, became more and more important for
accurate modeling of BJT ICs. A number of advanced BJT models have been
introduced to model emerging and second-order physical effects to provide
more precise simulation results [11]. These models include Vertical Bipolar
Inter Company model [12], Most Exquisite Transistor Model [13], and High
Current Model [14]. However, the SGP BJT model continued to be used in
circuit CAD because of its simplicity. Therefore, in this chapter only EM and
SGP models are described to provide readers the basic idea of BJT modeling.
In model derivations, the emphasis is placed on the understanding of the
effect being modeled along with the explanation of the required parameters.
Thus, in this chapter, we use a systematic methodology to derive SGP compact BJT model, starting from the basic EM compact BJT model that provides
an extremely useful understanding of the basic BJT operation.
11.2 Basic Features of BJTs
A silicon BJT structure is a sandwich of alternating type of doped silicon
layers. Depending on the sequence of layers, two types of BJTs are manufactured: npn and pnp. An npn-BJT is a sequence of n-p-n layers whereas a pnpBJT is a sequence of p-n-p layers. The npn-BJTs are most widely used in ICs
with BJT technologies. Again, the sequence of layers may be used vertically
to fabricate vertical BJTs or laterally referred to as the lateral BJTs. Figure 11.1
shows the basic structure of a vertical npn-BJT.
As shown in Figure 11.1b, the basic structure includes a heavily doped n+
emitter (E), a lightly doped n-epitaxial layer, a p-type base (B), and a heavily
doped n+ buried collector (C) on a p-type substrate. The p+ isolation regions are
used to isolate the adjacent devices in an IC chip. Typically, the isolation regions
are reverse-biased pn-junctions; however, in advanced BJTs, trench isolation is
used to increase the packing density of IC chips. The intrinsic device consists of
n-p-n vertical cross section as shown in Figure 11.1b. The one-dimensional (1D)
doping profile along the cutline from the surface of the active device is shown
in Figure 11.1c. Figure 11.2 shows a typical layout of an IC npn-BJT.
Figure 11.1c shows that the base region is nonuniformly doped. As a result,
a built-in electric field is set up to establish an equilibrium between the mobile
carriers attempt to diffuse away from the high concentration region and mobile
carriers pulled by the electric field (drift) of the fixed ionized donors (N d
+ )
or acceptors (N a
− ) left behind by mobile carriers. The built-in electric field is
obtained by setting: diffusion = drift (Equations 2.45 and 2.46).
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