368
Compact Models for Integrated Circuit Design
a. Draw the energy band diagrams with reference to the ideal
device structure for biasing conditions
i. V gs = 0 = V ds
ii. V gs < 0, V ds = 0
iii. V gs < 0, V ds < 0
Clearly label all relevant parameters;
b. Explain the operation of a pTFET device with reference to the
band diagram for each of the biasing conditions in part (a).
10.2 Consider the ideal all-silicon n-i-p TFET structure described in
exercise 10.1 to explain the interband tunneling mechanism in pTFET
devices.
a. Draw the energy band diagrams in the off-state with V gs = 0 = V ds
and on-state with biasing condition V gs < 0 and V ds < 0 so that a
tunneling window is created by overlapping bands at the sourcechannel junction. Clearly label all relevant parameters.
b. Explain the tunneling mechanism at the junction with reference
to the band diagrams in part (a).
c. Sketch the transfer characteristics (I ds − V gs ) of the device under
the biasing conditions in part (a) with reference to the band diagrams in part (a) (similar to Figure 10.3); explain your plots.
10.3 Complete the mathematical steps to derive Equation 10.7 for subthreshold swing in TFET devices. Identify the critical parameters
that can be used to optimize device performance for TFETs. Explain
with examples how these parameters can be used to improve current drivability in TFETs.
10.4 Compare the carrier transport mechanisms in TFETs and MOSFETs.
Explain why TFETs can offer lower S (<60 mV per decade of drain
current at room temperature) than that of MOSFETs using carrier
injection process and carrier statistics in each device.
10.5 Consider an all silicon n-i-p TFET device. Draw the energy
band diagrams.
a. At the onset of threshold voltage.
b. In the on-state.
Clearly label all relevant parameters and explain the device
operation.
10.6 The carrier transport and drive current in TFETs are independent
of gate length, L (i.e., length of the channel region). However, for
L < 20 nm, the p-i-n diode leakage current dominates increasing the
overall current flow in the device. Describe a simple technique to
model this additional current in short channel TFETs for circuit CAD.
Compact Models for Integrated Circuit Design
a. Draw the energy band diagrams with reference to the ideal
device structure for biasing conditions
i. V gs = 0 = V ds
ii. V gs < 0, V ds = 0
iii. V gs < 0, V ds < 0
Clearly label all relevant parameters;
b. Explain the operation of a pTFET device with reference to the
band diagram for each of the biasing conditions in part (a).
10.2 Consider the ideal all-silicon n-i-p TFET structure described in
exercise 10.1 to explain the interband tunneling mechanism in pTFET
devices.
a. Draw the energy band diagrams in the off-state with V gs = 0 = V ds
and on-state with biasing condition V gs < 0 and V ds < 0 so that a
tunneling window is created by overlapping bands at the sourcechannel junction. Clearly label all relevant parameters.
b. Explain the tunneling mechanism at the junction with reference
to the band diagrams in part (a).
c. Sketch the transfer characteristics (I ds − V gs ) of the device under
the biasing conditions in part (a) with reference to the band diagrams in part (a) (similar to Figure 10.3); explain your plots.
10.3 Complete the mathematical steps to derive Equation 10.7 for subthreshold swing in TFET devices. Identify the critical parameters
that can be used to optimize device performance for TFETs. Explain
with examples how these parameters can be used to improve current drivability in TFETs.
10.4 Compare the carrier transport mechanisms in TFETs and MOSFETs.
Explain why TFETs can offer lower S (<60 mV per decade of drain
current at room temperature) than that of MOSFETs using carrier
injection process and carrier statistics in each device.
10.5 Consider an all silicon n-i-p TFET device. Draw the energy
band diagrams.
a. At the onset of threshold voltage.
b. In the on-state.
Clearly label all relevant parameters and explain the device
operation.
10.6 The carrier transport and drive current in TFETs are independent
of gate length, L (i.e., length of the channel region). However, for
L < 20 nm, the p-i-n diode leakage current dominates increasing the
overall current flow in the device. Describe a simple technique to
model this additional current in short channel TFETs for circuit CAD.