15
Introduction to Compact Models
1.3 Motivation for Compact Modeling
The major motivation for the use of compact model for circuit CAD in the
semiconductor industry is the cost-effective and efficient design optimization of IC products [137] in EDA environment. The use of compact models in
circuit CAD allows optimization of circuit performance for robust IC chip
design. This optimization is a complex task due to the increasing complexities of the scaled MOSFET devices and technology. The continuous scaling
of CMOS devices to sub-100 nm regime has resulted in higher device density, faster circuit speed, and lower power dissipation. Many new physical
phenomena such as SCE and reverse SCE (RSCE), channel length modulation, drain-induced barrier lowering, remote surface roughness scattering, mobility degradation, impact ionization, band-to-band tunneling,
velocity overshoot, self-heating, channel quantization, polysilicon depletion, RF behaviors, NQS effects, and discrete dopants become significant
as the device dimension approaches its physical limit [51,55]. Thus, intuitive analysis of the performance of nanoscale VLSI circuits using first principle is no longer possible whereas trial-and-error experimentations using
breadboarding prototype [27] to build and characterize advanced IC chips
are time consuming and expensive. In addition, advanced VLSI circuits
with scaled devices are susceptible to process variability, causing device
and circuit performance variability [5]. As a result, the statistical analysis of
circuits is critical to develop advanced VLSI chips. Therefore, the compact
models are the desirable alternative for cost-effective and efficient design of
robust VLSI circuits, analysis of statistical device performance, analysis of
yield, and so on.
Again, by the introduction of the SPICE program from Berkeley in 1975,
the circuit simulator became a useful design tool, essentially replacing the
breadboarding of prototypes [27]. However, for accurate circuit analysis,
compact device models are required. Thus, the widespread use of circuit
simulation also motivated the early development and use of compact model
for IC device analysis. For today’s circuit design, the major motivations for
compact modeling include:
1. Circumventing the inadequate conventional manual techniques for
design and analysis of today’s complex VLSI circuits consisting of
billions of nanoscale devices
2. Designing an IC chip under the worst-case conditions so that manufacturing tolerances can be incorporated into the design, thus ensuring the target production yield of the chip
3. Performing statistical analysis to optimize circuits for process
variability–induced circuit performance variability, and also ensuring the target production yield of the chip
Introduction to Compact Models
1.3 Motivation for Compact Modeling
The major motivation for the use of compact model for circuit CAD in the
semiconductor industry is the cost-effective and efficient design optimization of IC products [137] in EDA environment. The use of compact models in
circuit CAD allows optimization of circuit performance for robust IC chip
design. This optimization is a complex task due to the increasing complexities of the scaled MOSFET devices and technology. The continuous scaling
of CMOS devices to sub-100 nm regime has resulted in higher device density, faster circuit speed, and lower power dissipation. Many new physical
phenomena such as SCE and reverse SCE (RSCE), channel length modulation, drain-induced barrier lowering, remote surface roughness scattering, mobility degradation, impact ionization, band-to-band tunneling,
velocity overshoot, self-heating, channel quantization, polysilicon depletion, RF behaviors, NQS effects, and discrete dopants become significant
as the device dimension approaches its physical limit [51,55]. Thus, intuitive analysis of the performance of nanoscale VLSI circuits using first principle is no longer possible whereas trial-and-error experimentations using
breadboarding prototype [27] to build and characterize advanced IC chips
are time consuming and expensive. In addition, advanced VLSI circuits
with scaled devices are susceptible to process variability, causing device
and circuit performance variability [5]. As a result, the statistical analysis of
circuits is critical to develop advanced VLSI chips. Therefore, the compact
models are the desirable alternative for cost-effective and efficient design of
robust VLSI circuits, analysis of statistical device performance, analysis of
yield, and so on.
Again, by the introduction of the SPICE program from Berkeley in 1975,
the circuit simulator became a useful design tool, essentially replacing the
breadboarding of prototypes [27]. However, for accurate circuit analysis,
compact device models are required. Thus, the widespread use of circuit
simulation also motivated the early development and use of compact model
for IC device analysis. For today’s circuit design, the major motivations for
compact modeling include:
1. Circumventing the inadequate conventional manual techniques for
design and analysis of today’s complex VLSI circuits consisting of
billions of nanoscale devices
2. Designing an IC chip under the worst-case conditions so that manufacturing tolerances can be incorporated into the design, thus ensuring the target production yield of the chip
3. Performing statistical analysis to optimize circuits for process
variability–induced circuit performance variability, and also ensuring the target production yield of the chip