14
Compact Models for Integrated Circuit Design
The bulk voltage referencing makes the EKV model symmetric [118–120] and
preserves the symmetry property with reference to effects such as velocity
saturation and nonuniform doping in the longitudinal direction [121]. The
EKV model uses normalized Q i at the source and drain ends to determine
all the important MOSFET variables including the current [118,122], the terminal charges [123], the transcapacitances [123–125], the admittances, the
transadmittances, [125], and the thermal noise, including the induced-gate
noise [126,127].
It is shown that in the charge-based EKV model, Q i linearization offers a
direct, simple relation between the surface potential f s and Q i [118,122,128].
The EKV model has been evolved into a full featured scalable compact MOS
model that includes all the major effects that have to be accounted for in
deep submicron CMOS technologies [129–131]. The model has also been
extended to double-gate device architectures using the EKV charge-based
approach [132].
In 2003, He et al. reported the charge-based BSIM5 model that uses a
single set of equations to calculate terminal charges throughout all the
bias regions [104,133]. The BSIM5 Q i equation is derived directly from the
solution of Poisson’s equation in terms of f s in contrast to the conventional
charge-based models [16,102] to obtain the final explicit function relating Q i
with MOS terminal voltages. The core BSIM5 model is derived assuming
gradual channel and constant quasi-Fermi level to the channel current, I ds
in terms of Q i at the source and drain ends. The I ds equation includes the
diffusion and drift components in a very simplified form. The model is
reported to offer symmetry, continuity, scalability, and computational efficiency with a minimal number of parameters. It can easily incorporate shortchannel, nonuniform doping, and numerous other physical effects such as
polydepletion, velocity saturation, and velocity overshoot to accurately
model subtle details of the device behaviors including current saturation and
QM effect. It is also reported that BSIM5 core model can be easily extended to
model nonclassical devices such as ultrathin body SOI and multigate devices
including FinFETs [134].
In late 2010, the BSIM group started the development of BSIM6 core
model [4]. The basic objective of BSIM6 development is to solve the symmetry issue of BSIM4 while maintaining BSIM4’s accuracy, speed, and user
support. The core BSIM6 has been derived using the reported charge-based
approach [99,128,131,133]. The main features of BSIM6 include: smooth and
continuous behaviors of I–V and C–V and their derivatives; continuity around
V ds = 0 and symmetry issue; excellent scalability with geometry, bias, and
temperature; robust and physical behavior; excellent analog and RF modeling capability; and maintaining BSIM4 user experience [135]. In May 2013,
BSIM6 has been selected and released as the industry-standard compact model
for the existing as well as advanced planar CMOS technology nodes [48].
The model has been coded in Verilog-A and implemented in major EDA
environment [136].
Compact Models for Integrated Circuit Design
The bulk voltage referencing makes the EKV model symmetric [118–120] and
preserves the symmetry property with reference to effects such as velocity
saturation and nonuniform doping in the longitudinal direction [121]. The
EKV model uses normalized Q i at the source and drain ends to determine
all the important MOSFET variables including the current [118,122], the terminal charges [123], the transcapacitances [123–125], the admittances, the
transadmittances, [125], and the thermal noise, including the induced-gate
noise [126,127].
It is shown that in the charge-based EKV model, Q i linearization offers a
direct, simple relation between the surface potential f s and Q i [118,122,128].
The EKV model has been evolved into a full featured scalable compact MOS
model that includes all the major effects that have to be accounted for in
deep submicron CMOS technologies [129–131]. The model has also been
extended to double-gate device architectures using the EKV charge-based
approach [132].
In 2003, He et al. reported the charge-based BSIM5 model that uses a
single set of equations to calculate terminal charges throughout all the
bias regions [104,133]. The BSIM5 Q i equation is derived directly from the
solution of Poisson’s equation in terms of f s in contrast to the conventional
charge-based models [16,102] to obtain the final explicit function relating Q i
with MOS terminal voltages. The core BSIM5 model is derived assuming
gradual channel and constant quasi-Fermi level to the channel current, I ds
in terms of Q i at the source and drain ends. The I ds equation includes the
diffusion and drift components in a very simplified form. The model is
reported to offer symmetry, continuity, scalability, and computational efficiency with a minimal number of parameters. It can easily incorporate shortchannel, nonuniform doping, and numerous other physical effects such as
polydepletion, velocity saturation, and velocity overshoot to accurately
model subtle details of the device behaviors including current saturation and
QM effect. It is also reported that BSIM5 core model can be easily extended to
model nonclassical devices such as ultrathin body SOI and multigate devices
including FinFETs [134].
In late 2010, the BSIM group started the development of BSIM6 core
model [4]. The basic objective of BSIM6 development is to solve the symmetry issue of BSIM4 while maintaining BSIM4’s accuracy, speed, and user
support. The core BSIM6 has been derived using the reported charge-based
approach [99,128,131,133]. The main features of BSIM6 include: smooth and
continuous behaviors of I–V and C–V and their derivatives; continuity around
V ds = 0 and symmetry issue; excellent scalability with geometry, bias, and
temperature; robust and physical behavior; excellent analog and RF modeling capability; and maintaining BSIM4 user experience [135]. In May 2013,
BSIM6 has been selected and released as the industry-standard compact model
for the existing as well as advanced planar CMOS technology nodes [48].
The model has been coded in Verilog-A and implemented in major EDA
environment [136].