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Modeling Process Variability in Scaled MOSFETs
8.5.3 Determination of Variance for Process Variability-Sensitive
Compact Model Parameters
The variance σM of the compact model parameter M due to process variability is included to the mean (TT) value M 0 to model the impact of process
variability on VLSI circuit performance.
8.5.3.1 Variance of Local Process Variability-Sensitive Compact
Model Parameters
For a large number of samples ∆M mismatch between paired transistors is
described by standard normal distribution, N
M mismatch
0, σ ∆
(
) , where the variance σ ∆M mismatch is given by: σ ∆M mismatch pair
M
A
WL
≅
/
as described in Section
8.3.1 [43,44], where the parameter A M is a technology-dependent constant
of ∆M and is extracted from ∆M i versus 1/ WL
(
) plot for a large number
(i = 1, 2, 3, … l) of sample ET data [1,43,44]. Thus, for the compact model
parameter V TH0 , the variance of ∆V TH0 between two paired transistors is
given by:
σ ∆V
A
WL
TH pair
vt
0
≅
(8.18)
where:
A vt is the area dependent constant of ΔV TH 0
Typically, each mismatch parameter ΔVTH0, ΔXW, ΔXL, ΔT ox , ΔU0, and ΔK1
can be represented by an expression similar to Equation 8.16. Again, since
∆M i is random and independent, the correlation ρ ∆
∆
M M
i
i
,
+
(
)=
1
0 [43].
Then, for a single device we get
σ
σ
M
A
WL
mismatch
M
M
i
=
=
1
2
1
2
∆
(8.19)
In Equation 8.19, σM mismatch represents the variance of ∆M due to within-die
stochastic process variability. Thus, the variance of ∆V TH0 is given by
σ
σ
V
A
WL
TH mismatch
V
vt
TH
0
1
2
1
2
0
,
=
=
∆
(8.20)
For statistical compact modeling, σM mismatch for each variability-sensitive
parameter is added to the corresponding M 0 to compute mismatch between
paired transistors. Typically, for each M, A M is extracted from Pelgrom’s
plot from a large set of measurement data. For next generation technology
development, a large set of data can be obtained by numerical process and
device CAD to compute σM mismatch for each variability-sensitive compact
model parameters [51–55].