279
Compact MOSFET Models for RF Applications
the NQS effect from the bulk charge is negligible and does not significantly
impact small signal simulation. However, the body current can be included
by partitioning Q def between the gate and the body [35,49].
7.4 Modeling Parasitic Elements for RF Applications
With the continuous scaling down of CMOS technologies to the nanoscale
regime, RF circuits are realized in a standard CMOS process [50]. Therefore,
a compact model for circuit CAD that is valid for a broad range of bias conditions, device sizes, and operating frequencies is of utmost importance. The
widely used RF modeling approach is to build subcircuits based on MOSFET
models that are suitable for analog/digital applications [40,51–55]. In the
subcircuit, parasitic elements around gate, source, drain, and substrate as
shown in Figure 7.7 are added to improve the accuracy of the model at high
frequencies [40]. An important part of RF modeling is to establish physical
and scalable model equations for the parasitic elements at the source, drain,
gate, and substrate. The scalability of the intrinsic device is ensured by the
core model library developed using the target compact model discussed in
Chapters 4 and 5. We will now discuss the techniques to model the gate and
substrate resistances for RF and analog applications.
7.4.1 Modeling Gate Resistance
At any low frequency, the gate resistance of a MOSFET can be calculated
from the sheet resistance of the gate material and is given by
G
D
S
R s
C jsb
C jdb
R dsb
R db
R sb
B
R g
R d
FIGURE 7.7
A subcircuit with parasitic elements added to an intrinsic MOSFET model for RF analysis.
(Data from Y. Cheng et al., Proceedings of the ICSICT, 416–419, 1998.)
Compact MOSFET Models for RF Applications
the NQS effect from the bulk charge is negligible and does not significantly
impact small signal simulation. However, the body current can be included
by partitioning Q def between the gate and the body [35,49].
7.4 Modeling Parasitic Elements for RF Applications
With the continuous scaling down of CMOS technologies to the nanoscale
regime, RF circuits are realized in a standard CMOS process [50]. Therefore,
a compact model for circuit CAD that is valid for a broad range of bias conditions, device sizes, and operating frequencies is of utmost importance. The
widely used RF modeling approach is to build subcircuits based on MOSFET
models that are suitable for analog/digital applications [40,51–55]. In the
subcircuit, parasitic elements around gate, source, drain, and substrate as
shown in Figure 7.7 are added to improve the accuracy of the model at high
frequencies [40]. An important part of RF modeling is to establish physical
and scalable model equations for the parasitic elements at the source, drain,
gate, and substrate. The scalability of the intrinsic device is ensured by the
core model library developed using the target compact model discussed in
Chapters 4 and 5. We will now discuss the techniques to model the gate and
substrate resistances for RF and analog applications.
7.4.1 Modeling Gate Resistance
At any low frequency, the gate resistance of a MOSFET can be calculated
from the sheet resistance of the gate material and is given by
G
D
S
R s
C jsb
C jdb
R dsb
R db
R sb
B
R g
R d
FIGURE 7.7
A subcircuit with parasitic elements added to an intrinsic MOSFET model for RF analysis.
(Data from Y. Cheng et al., Proceedings of the ICSICT, 416–419, 1998.)