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Compact Models for Integrated Circuit Design
interface to x = t si  = 30 nm at the bottom gate Si/SiO 2 interface.
Clearly define and label all relevant data points such as
i. Surface potential
ii. Fermi potential
iii. Depletion width
iv. Inversion layer thickness
v. Energy levels.
d. Calculate and plot the potential into the silicon from the top
gate to the bottom gate at strong inversion for the top gate only.
Repeat the calculation for the bottom gate only and plot on the
same X–Y graph. Show the overall potential distribution from
the top gate to the bottom gate when both gates are considered.
Clearly define and label all relevant data points. Explain.
3.7 FinFETs with intrinsic or very lightly doped channel doping
shown in Figure E3.2 are the most realistic double gate MOSFETs.
Consider a simple FinFET capacitor fabricated on a lightly doped
p-type substrate with N a  = 3 × 10 15  cm –3 , T fin  = 20 nm, H fin  = 50 nm,
L g  = 50 nm, T ox  = 15 nm, and gates connected together, as shown in
Figure E3.2. (Ignore the effect of Source/Drain on the MOS capacitor
system).
a. Calculate the depletion width of silicon at strong inversion.
b. Calculate the width of the inversion layer at strong inversion.
Assume that the inversion layer thickness for a single gate is
given by
Bottom metal gate
Top metal gate
Gate oxide
Silicon
Gate oxide
T ox
L g
T ox
t si
FIGURE E3.1
An ideal double gate MOS capacitance structure.