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Compact Models for Integrated Circuit Design
metal or degenerately doped polysilicon or a combination of polysilicon
and silicide (e.g., TiSi 2 , CoSi 2 ) is formed on the top of the gate dielectric by
masking, photolithography, and annealing processes. The body electrode
is obtained by deposited metal to achieve an ohmic contact. If the substrate
conducts sufficiently to support the displacement currents, the structure in
Figure 3.1 forms a parallel-plate capacitor with G as one electrode, B as the
second electrode, and SiO 2 as the dielectric. This is referred to as the MOS
capacitor system. This system is in thermal equilibrium with applied DC
bias, and if the change in voltage is sufficiently slow, it is approximated to
be a constant. Thus, from the parallel-plate capacitance formulation, we
can write the oxide capacitance ( C ox ) per unit area between the metal and
silicon surface as:
C
K
T
ox
ox
ox
=
ε 0
(3.1)
where:
ε 0 is the permittivity of free space or vacuum
K ox is the dielectric constant of oxide
T ox is the gate oxide thickness
In order to study the behavior of MOS capacitor system, let us consider
the metal, oxide, and semiconductor (p-type silicon) as three separate
materials, that is, materials before brought into contact. The energy band
diagram of each material is shown separately in Figure 3.2. In Figure 3.2,
E 0 denotes a convenient reference potential energy level, which is the vacuum or free electron energy level. In reality, E 0 is the level at which the
Coulombic potential of an isolated positive charge becomes zero. It is to
be noted that the reported value of bandgap energy for SiO 2 layer is in the
range of 8.0–9.0 eV [1–3]. In Figure 3.2, we have used 8.0 eV as the bandgap
energy for SiO 2 to discuss the behavior of MOS capacitor. The other characteristic parameters of the three materials in Figure 3.2 are defined in the
next subsection.
Silicon dioxide (SiO 2 )
G
B
Gate electrode
(Metal or polysilicon)
N a = Acceptor
concentration
p-Substrate, N a
T ox
FIGURE 3.1
2D cross section of an ideal MOS capacitor structure fabricated on a uniformly doped p-type
substrate with doping concentration, N a ; here G and B denote the gate and body electrodes for
applied biases to the gate and substrate, respectively.
Compact Models for Integrated Circuit Design
metal or degenerately doped polysilicon or a combination of polysilicon
and silicide (e.g., TiSi 2 , CoSi 2 ) is formed on the top of the gate dielectric by
masking, photolithography, and annealing processes. The body electrode
is obtained by deposited metal to achieve an ohmic contact. If the substrate
conducts sufficiently to support the displacement currents, the structure in
Figure 3.1 forms a parallel-plate capacitor with G as one electrode, B as the
second electrode, and SiO 2 as the dielectric. This is referred to as the MOS
capacitor system. This system is in thermal equilibrium with applied DC
bias, and if the change in voltage is sufficiently slow, it is approximated to
be a constant. Thus, from the parallel-plate capacitance formulation, we
can write the oxide capacitance ( C ox ) per unit area between the metal and
silicon surface as:
C
K
T
ox
ox
ox
=
ε 0
(3.1)
where:
ε 0 is the permittivity of free space or vacuum
K ox is the dielectric constant of oxide
T ox is the gate oxide thickness
In order to study the behavior of MOS capacitor system, let us consider
the metal, oxide, and semiconductor (p-type silicon) as three separate
materials, that is, materials before brought into contact. The energy band
diagram of each material is shown separately in Figure 3.2. In Figure 3.2,
E 0 denotes a convenient reference potential energy level, which is the vacuum or free electron energy level. In reality, E 0 is the level at which the
Coulombic potential of an isolated positive charge becomes zero. It is to
be noted that the reported value of bandgap energy for SiO 2 layer is in the
range of 8.0–9.0 eV [1–3]. In Figure 3.2, we have used 8.0 eV as the bandgap
energy for SiO 2 to discuss the behavior of MOS capacitor. The other characteristic parameters of the three materials in Figure 3.2 are defined in the
next subsection.
Silicon dioxide (SiO 2 )
G
B
Gate electrode
(Metal or polysilicon)
N a = Acceptor
concentration
p-Substrate, N a
T ox
FIGURE 3.1
2D cross section of an ideal MOS capacitor structure fabricated on a uniformly doped p-type
substrate with doping concentration, N a ; here G and B denote the gate and body electrodes for
applied biases to the gate and substrate, respectively.