Microcontrollers
583
14.5.1.3 80C31RA
+ /8XC51RA
+ /RB
+ /RC
+ (Dallas Semiconductor and Other
manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 512
bytes (RAM).
14.5.1.4 8XC51RD
+ (Dallas Semiconductor and Other Manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 64K (ROM) and 1024 bytes
(RAM).
14.5.1.5 80C32/8XC52/54/58 (Dallas Semiconductor and Other Manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 256
bytes (RAM).
14.5.1.6 89C51 (ATMEL and Other Manufacturers)
Microcontroller-related Features
MCS-51 architecture, CMOS technology, 4K × 8 of in-system reprogrammable ROM, 128 × 8 internal
RAM, memory addressing capability of 64K (ROM and RAM), special-function registers, six interrupt
sources, two power-saving modes (IDLE and POWER DOWN modes), a clock speed range of 0–24
MHz, low EMI (inhibit ALE), three package style options (40-pin dual in-line, 44-pin plastic leaded
chip carrier and 44-pin plastic quad flat pack) and compatible with the industry-standard MCS-51
instruction set and pin-out.
Peripheral-related Features
Two 16-bit counters/timers, 32 programmable I/O lines and a programmable serial channel.
Architecture and Pin Connection Diagram
The architecture and pin connection diagram are the same as those given earlier for the case of the
80C51 family of microcontrollers in Fig. 14.16 (architecture) and Fig. 14.17 (pin connection diagram).
14.5.1.7 68HC05 Family of Microcontrollers (Freescale Semiconductor)
Microcontroller-related Features
Fully static chip design using a standard eight-bit M68HC05 core, a clock speed of 4 MHz, 920
bytes of on-chip RAM, 32K of ROM, 7932 bytes of EEPROM (maximum values across the family of
devices), power-saving WAIT mode and available in 40-pin DIP and 42-pin SDIP package styles.
Peripheral-related Features
Two serial interface channels, a multifunction timer with periodic interrupt, eight A/D converter
channels, three PWM channels and 80 I/O lines (maximum values across the family of devices).
583
14.5.1.3 80C31RA
+ /8XC51RA
+ /RB
+ /RC
+ (Dallas Semiconductor and Other
manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 512
bytes (RAM).
14.5.1.4 8XC51RD
+ (Dallas Semiconductor and Other Manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 64K (ROM) and 1024 bytes
(RAM).
14.5.1.5 80C32/8XC52/54/58 (Dallas Semiconductor and Other Manufacturers)
The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 256
bytes (RAM).
14.5.1.6 89C51 (ATMEL and Other Manufacturers)
Microcontroller-related Features
MCS-51 architecture, CMOS technology, 4K × 8 of in-system reprogrammable ROM, 128 × 8 internal
RAM, memory addressing capability of 64K (ROM and RAM), special-function registers, six interrupt
sources, two power-saving modes (IDLE and POWER DOWN modes), a clock speed range of 0–24
MHz, low EMI (inhibit ALE), three package style options (40-pin dual in-line, 44-pin plastic leaded
chip carrier and 44-pin plastic quad flat pack) and compatible with the industry-standard MCS-51
instruction set and pin-out.
Peripheral-related Features
Two 16-bit counters/timers, 32 programmable I/O lines and a programmable serial channel.
Architecture and Pin Connection Diagram
The architecture and pin connection diagram are the same as those given earlier for the case of the
80C51 family of microcontrollers in Fig. 14.16 (architecture) and Fig. 14.17 (pin connection diagram).
14.5.1.7 68HC05 Family of Microcontrollers (Freescale Semiconductor)
Microcontroller-related Features
Fully static chip design using a standard eight-bit M68HC05 core, a clock speed of 4 MHz, 920
bytes of on-chip RAM, 32K of ROM, 7932 bytes of EEPROM (maximum values across the family of
devices), power-saving WAIT mode and available in 40-pin DIP and 42-pin SDIP package styles.
Peripheral-related Features
Two serial interface channels, a multifunction timer with periodic interrupt, eight A/D converter
channels, three PWM channels and 80 I/O lines (maximum values across the family of devices).