Microcontrollers
579
Fetch
Instruction
Decode
Instruction
Fetch
Operands
Execute
Instruction
Write
Results
Figure 14.15 Pipelined architecture.
14.3.3.4 Pipeline Architecture
In pipelined architecture, as shown in Fig. 14.15, there are separate hardware stages for execution
of different steps involved in execution of an instruction. These different steps include fetching an
instruction from memory, decoding the instruction, fetching instruction operands from memory or
registers, executing the instruction and then finally placing the result back on the memory. Pipelining
allows these stages to overlap and perform with parallelism. The overall result is that the execution of
an instruction is completed on every clock cycle. Instructions in a pipelined architecture are usually
simple instructions that can be implemented within a single stage. These simple instructions act as
building blocks for more complex instructions.
14.4 Power-Saving Modes
Power consumption is one of the important issues in battery-powered devices. Most microcontrollers
come with various power-saving features. For a given application requirement, designers use these
features to keep the power consumption down to an optimum value without compromising the
operational requirements of the device. It may be mentioned here that not all modes are for power
saving. Some microcontrollers support in-circuit debugging. As an example, some of the power-saving
modes available with the 80C51 family of microcontrollers are briefly outlined in the following
paragraphs.
The stop clock mode allows the clock oscillator to be stopped or the clock speed to be reduced to
as low as 0 MHz. When the oscillator is stopped, the special-function registers and RAM retain their
values. This mode allows reduced power consumption by lowering the clock frequency to any value.
The idle mode is another power-saving mode available with the 80C51 family of microcontrollers.
In this mode, the processor puts itself to sleep while all on-chip peripheral components stay active. The
processor contents, the on-chip RAM and all special-function registers remain intact during the idle
mode. The instruction that invokes this mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The idle mode can be terminated by either an enabled interrupt
or by a hardware reset. By an enabled interrupt, the process is picked up at the interrupt service routine
and continued. Hardware reset starts the processor in the same manner as it does on a power-on reset.
The power down mode is recommended for the lowest power consumption. When this mode is
enabled, the oscillator stops and the instruction that invokes the power down mode is the last instruction
executed. Special-function registers and on-chip RAM retain their values down to a V CC amplitude of
2.0 V. V CC must be brought to the minimum specified operating voltage before this mode is deactivated.
Either a hardware reset or an external interrupt can be used to terminate the power down mode. While a
hardware reset redefines all the special-function registers and retains on-chip RAM values, an external
interrupt allows both special-function registers and the on-chip RAM to retain their values. For proper
termination of the power-down mode, a reset or external interrupt should not be executed unless V CC is
restored to its normal operating level and also has been held active long enough for the oscillator to
start and stabilize.
579
Fetch
Instruction
Decode
Instruction
Fetch
Operands
Execute
Instruction
Write
Results
Figure 14.15 Pipelined architecture.
14.3.3.4 Pipeline Architecture
In pipelined architecture, as shown in Fig. 14.15, there are separate hardware stages for execution
of different steps involved in execution of an instruction. These different steps include fetching an
instruction from memory, decoding the instruction, fetching instruction operands from memory or
registers, executing the instruction and then finally placing the result back on the memory. Pipelining
allows these stages to overlap and perform with parallelism. The overall result is that the execution of
an instruction is completed on every clock cycle. Instructions in a pipelined architecture are usually
simple instructions that can be implemented within a single stage. These simple instructions act as
building blocks for more complex instructions.
14.4 Power-Saving Modes
Power consumption is one of the important issues in battery-powered devices. Most microcontrollers
come with various power-saving features. For a given application requirement, designers use these
features to keep the power consumption down to an optimum value without compromising the
operational requirements of the device. It may be mentioned here that not all modes are for power
saving. Some microcontrollers support in-circuit debugging. As an example, some of the power-saving
modes available with the 80C51 family of microcontrollers are briefly outlined in the following
paragraphs.
The stop clock mode allows the clock oscillator to be stopped or the clock speed to be reduced to
as low as 0 MHz. When the oscillator is stopped, the special-function registers and RAM retain their
values. This mode allows reduced power consumption by lowering the clock frequency to any value.
The idle mode is another power-saving mode available with the 80C51 family of microcontrollers.
In this mode, the processor puts itself to sleep while all on-chip peripheral components stay active. The
processor contents, the on-chip RAM and all special-function registers remain intact during the idle
mode. The instruction that invokes this mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The idle mode can be terminated by either an enabled interrupt
or by a hardware reset. By an enabled interrupt, the process is picked up at the interrupt service routine
and continued. Hardware reset starts the processor in the same manner as it does on a power-on reset.
The power down mode is recommended for the lowest power consumption. When this mode is
enabled, the oscillator stops and the instruction that invokes the power down mode is the last instruction
executed. Special-function registers and on-chip RAM retain their values down to a V CC amplitude of
2.0 V. V CC must be brought to the minimum specified operating voltage before this mode is deactivated.
Either a hardware reset or an external interrupt can be used to terminate the power down mode. While a
hardware reset redefines all the special-function registers and retains on-chip RAM values, an external
interrupt allows both special-function registers and the on-chip RAM to retain their values. For proper
termination of the power-down mode, a reset or external interrupt should not be executed unless V CC is
restored to its normal operating level and also has been held active long enough for the oscillator to
start and stabilize.