Counters and Registers
435
CLK(UP)
CLK(DOWN)
TCU
TCD
P3 P2 P1 P0
Q3
Q2
Q1
Q0
Lower Order Counter
CLK(UP)
CLK(DOWN)
TCU
TCD
P3 P2 P1 P0
Q3
Q2
Q1
Q0
Higher Order Counter
PL
PL
CLK(UP)
CLK(DOWN)
TCU
TCD
P3 P2 P1 P0
Q3
Q2
Q1
Q0
Lower Order Counter
CLK(UP)
CLK(DOWN)
TCU
TCD
P3 P2 P1 P0
Q3
Q2
Q1
Q0
Higher Order Counter
PL
PL
(a)
(b)
Figure 11.20 Cascading binary counters.
and the process continues. If it is desired to build a multistage DOWN counter, all counters are wired
as DOWN counters, the clock is applied to the clock input of the lowest-order counter and the terminal
count DOWN (TCD), also called the borrow-out (B o , of the lowest-order counter is applied to the
clock input of the next higher counter stage. The process continues in the same fashion, with the TCD
output of the second stage feeding the clock input of the third stage and so on. The modulus of the
multistage counter arrangement equals the product of the moduli of individual stages. Figures 11.20(a)
and (b) respectively show two-stage arrangements of four-bit synchronous UP and DOWN counters
respectively.
11.10.2 Cascading BCD Counters
BCD counters are used when the application involves the counting of pulses and the result of counting
is to be displayed in decimal. A single-stage BCD counter counts from 0000 (decimal equivalent
‘0’) to 1001 (decimal equivalent ‘9’) and thus is capable of counting up to a maximum of nine
pulses. The output in a BCD counter is in binary coded decimal (BCD) form. The BCD output needs