420
Digital Electronics
Q 0
FF0
J
K
Q 1
FF1
J
K
Q 2
FF2
J
K
Q 3
FF3
J
K
1.2MHZ
1
Clk
Cl
Clk
Cl
Clk
Cl
Clk
Cl
Figure 11.5 Example 11.3.
Solution
The counter is required to go to the 111 state from the 000 state with the first relevant clock
transition. The second transition brings it back to the 000 state. That is, the three flip-flops toggle
from logic ‘0’ state to logic ‘1’ state with every odd-numbered clock transition, and also the three
flip-flops toggle from logic ‘1’ state to logic ‘0’ state with every even-numbered clock transition.
Figure 11.6(a) shows the arrangement. The PRESET inputs of the three flip-flops have been tied to
the NAND output whose inputs are Q A Q B and Q C Every time the counter is in the 000 state and
is clocked, the NAND output momentarily goes from logic ‘1’ state to logic ‘0’ state, thus presetting
the Q A Q B and Q C outputs to the logic ‘1’ state. The timing waveforms as shown in Fig. 11.6(b) are
self-explanatory.
The Q A , Q B and Q C waveforms are identical, and each of them has a frequency of f c /2, where f c is
the clock frequency.
Example 11.5
Refer to the binary ripple counter arrangement of Fig. 11.7. Write its count sequence if it is initially
in the 0000 state. Also draw the timing waveforms.
Solution
The counter is initially in the 0000 state. With the first clock pulse, Q 0 toggles from the ‘0’ to the ‘1’
state, which means Q 0 toggles from ‘1’ to ‘0’. Since Q 0 here feeds the clock input of next flip-flop,
flip-flop FF1 also toggles. Thus, Q 1 goes from ‘0’ to ‘1’. Since flip-flops FF2 and FF3 are also clocked
from complementary outputs of their immediately preceding flip-flops, they also toggle. Thus, the
counter moves from the 0000 state to the 1111 state with the first clock pulse.
With the second clock pulse, Q 0 toggles again, but the other flip-flops remain unaffected for
obvious reasons and the counter is in the 1110 state. With subsequent clock pulses, the counter
keeps counting downwards by one LSB at a time until it reaches 0000 again, after which the process
repeats. The count sequence is given as 0000, 1111, 1110, 1101,1100, 1011, 1010, 1001, 1000,
Digital Electronics
Q 0
FF0
J
K
Q 1
FF1
J
K
Q 2
FF2
J
K
Q 3
FF3
J
K
1.2MHZ
1
Clk
Cl
Clk
Cl
Clk
Cl
Clk
Cl
Figure 11.5 Example 11.3.
Solution
The counter is required to go to the 111 state from the 000 state with the first relevant clock
transition. The second transition brings it back to the 000 state. That is, the three flip-flops toggle
from logic ‘0’ state to logic ‘1’ state with every odd-numbered clock transition, and also the three
flip-flops toggle from logic ‘1’ state to logic ‘0’ state with every even-numbered clock transition.
Figure 11.6(a) shows the arrangement. The PRESET inputs of the three flip-flops have been tied to
the NAND output whose inputs are Q A Q B and Q C Every time the counter is in the 000 state and
is clocked, the NAND output momentarily goes from logic ‘1’ state to logic ‘0’ state, thus presetting
the Q A Q B and Q C outputs to the logic ‘1’ state. The timing waveforms as shown in Fig. 11.6(b) are
self-explanatory.
The Q A , Q B and Q C waveforms are identical, and each of them has a frequency of f c /2, where f c is
the clock frequency.
Example 11.5
Refer to the binary ripple counter arrangement of Fig. 11.7. Write its count sequence if it is initially
in the 0000 state. Also draw the timing waveforms.
Solution
The counter is initially in the 0000 state. With the first clock pulse, Q 0 toggles from the ‘0’ to the ‘1’
state, which means Q 0 toggles from ‘1’ to ‘0’. Since Q 0 here feeds the clock input of next flip-flop,
flip-flop FF1 also toggles. Thus, Q 1 goes from ‘0’ to ‘1’. Since flip-flops FF2 and FF3 are also clocked
from complementary outputs of their immediately preceding flip-flops, they also toggle. Thus, the
counter moves from the 0000 state to the 1111 state with the first clock pulse.
With the second clock pulse, Q 0 toggles again, but the other flip-flops remain unaffected for
obvious reasons and the counter is in the 1110 state. With subsequent clock pulses, the counter
keeps counting downwards by one LSB at a time until it reaches 0000 again, after which the process
repeats. The count sequence is given as 0000, 1111, 1110, 1101,1100, 1011, 1010, 1001, 1000,