Flip-Flops and Related Devices
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(a) set-up time and hold time;
(b) propagation delay;
(c) maximum clock frequency.
7. Draw the truth table for the following types of flip-flop:
(a) a positive edge-triggered J -K flip-flop with active HIGH J and K inputs and active LOW
PRESET and CLEAR inputs;
(b) a negative edge-triggered J -K flip-flop with active LOW J and K inputs and active LOW
PRESET and CLEAR inputs.
8. What is meant by the race problem in flip-flops? How does a master–slave configuration help in
solving this problem?
9. Differentiate between a D flip-flop and a D latch.
10. Draw the function table for (a) a negative edge-triggered D flip-flop and (b) a D latch with an
active LOW ENABLE input.
11. With the help of a schematic arrangement, explain how a J -K flip-flop can be used as a (a) a D
flip-flop and (b) a T flip-flop.
12. With the help of a suitable circuit, briefly explain how a D flip-flop can be used to detect the
sequence of occurrence of edges of synchronous inputs.
Problems
1. A 100 kHz clock signal is applied to a J -K flip-flop with J = K = 1 .
(a) If the flip-flop has active HIGH J and K inputs and is negative edge triggered, determine the
frequency of the Q and Q outputs.
(b) If the flip-flop has active LOW J and K inputs and is positive edge triggered, what should the
frequency of the Q and Q outputs be? Assume that Q is initially ‘0’.
(a) Q output = 50 kHz, Q output = 50 kHz;
(b) both outputs remain in a logic ‘0’ state
2. In a Schmitt trigger inverter circuit, the two trip points are observed to occur at 1.8 and 2.8 V. At
what input voltage levels will this device make (a) HIGH-to-LOW transition and (b) LOW-to-HIGH
transition?
(a) 2.8 V; (b) 1.8 V
3. In the case of a presettable, clearable J -K flip-flop with active HIGH J and K inputs and active
LOW PRESET and CLEAR inputs, what would the Q output logic status be for the following input
conditions, assuming that Q is initially ‘0’, immediately after it is clocked?
(a) J = 1 , K = 0, PRESET = 1, CLEAR = 1;
(b) J = 1 , K = 1 , PRESET = 0, CLEAR = 1;
(c) J = 0, K = 1 , PRESET = 1, CLEAR = 0;
(d) J = K = 0, PRESET = 0, CLEAR = 1.
(a) 1; (b) 1; (c) 0; (d) 1
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(a) set-up time and hold time;
(b) propagation delay;
(c) maximum clock frequency.
7. Draw the truth table for the following types of flip-flop:
(a) a positive edge-triggered J -K flip-flop with active HIGH J and K inputs and active LOW
PRESET and CLEAR inputs;
(b) a negative edge-triggered J -K flip-flop with active LOW J and K inputs and active LOW
PRESET and CLEAR inputs.
8. What is meant by the race problem in flip-flops? How does a master–slave configuration help in
solving this problem?
9. Differentiate between a D flip-flop and a D latch.
10. Draw the function table for (a) a negative edge-triggered D flip-flop and (b) a D latch with an
active LOW ENABLE input.
11. With the help of a schematic arrangement, explain how a J -K flip-flop can be used as a (a) a D
flip-flop and (b) a T flip-flop.
12. With the help of a suitable circuit, briefly explain how a D flip-flop can be used to detect the
sequence of occurrence of edges of synchronous inputs.
Problems
1. A 100 kHz clock signal is applied to a J -K flip-flop with J = K = 1 .
(a) If the flip-flop has active HIGH J and K inputs and is negative edge triggered, determine the
frequency of the Q and Q outputs.
(b) If the flip-flop has active LOW J and K inputs and is positive edge triggered, what should the
frequency of the Q and Q outputs be? Assume that Q is initially ‘0’.
(a) Q output = 50 kHz, Q output = 50 kHz;
(b) both outputs remain in a logic ‘0’ state
2. In a Schmitt trigger inverter circuit, the two trip points are observed to occur at 1.8 and 2.8 V. At
what input voltage levels will this device make (a) HIGH-to-LOW transition and (b) LOW-to-HIGH
transition?
(a) 2.8 V; (b) 1.8 V
3. In the case of a presettable, clearable J -K flip-flop with active HIGH J and K inputs and active
LOW PRESET and CLEAR inputs, what would the Q output logic status be for the following input
conditions, assuming that Q is initially ‘0’, immediately after it is clocked?
(a) J = 1 , K = 0, PRESET = 1, CLEAR = 1;
(b) J = 1 , K = 1 , PRESET = 0, CLEAR = 1;
(c) J = 0, K = 1 , PRESET = 1, CLEAR = 0;
(d) J = K = 0, PRESET = 0, CLEAR = 1.
(a) 1; (b) 1; (c) 0; (d) 1