Flip-Flops and Related Devices
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10.9 Flip-Flop Timing Parameters
Certain timing parameters would be listed in the specification sheet of a flip-flop. Some of these
parameters, as we will see in the paragraphs to follow, are specific to the logic family to which the
flip-flop belongs. There are some parameters that have different values for different flip-flops belonging
to the same broad logic family. It is therefore important that one considers these timing parameters
before using a certain flip-flop in a given application. Some of the important ones are set-up and hold
times, propagation delay, clock pulse HIGH and LOW times, asynchronous input active pulse width,
clock transition time and maximum clock frequency.
10.9.1 Set-Up and Hold Times
The set-up time is the minimum time period for which the synchronous inputs (for example, R, S, J ,
K and DD and asynchronous inputs (for example, PRESET and CLEAR) must be stable prior to the
active clock transition for the flip-flop output to respond reliably at the clock transition. It is usually
denoted by t s (min) and is usually defined separately for synchronous and asynchronous inputs. As
an example, if in a J -K flip-flop the J and K inputs were to go to ‘1’ and ‘0’ respectively, and
if the flip-flop were negative edge triggered, the set-up time would be as shown in Fig. 10.43(a).
The set-up time in the case of 74ALS109A, which is a dual J -K positive edge-triggered flip-flop
belonging to the advanced low-power Schottky TTL logic family, is 15 ns. Also, the asynchronous
inputs, such as PRESET and CLEAR, if there, should be inactive prior to the clock transition for a
certain minimum time period if the outputs have to respond as per synchronous inputs. In the case
of 74ALS109A, the asynchronous input set-up time is 10 ns. The asynchronous input set-up time for
active low PRESET and CLEAR inputs is shown in Fig. 10.43(b), assuming a positive edge-triggered
flip-flop.
The hold time t H (min) is the minimum time period for which the synchronous inputs (R, S, J , K, DD
must remain stable in the desired logic state after the active clock transition for the flip-flop to respond
reliably. The same is depicted in Fig. 10.43(a) if the desired logic status for J and K inputs is ‘1’ and
‘0’ respectively and the flip-flop is negative edge triggered. The hold time for flip-flop 74ALS109A
is specified to be zero. To sum up, for a flip-flop to respond properly and reliably at the active clock
transition, the synchronous inputs must be stable in their intended logic states and the asynchronous
inputs must be stable in their inactive states for at least a time period equal to the specified minimum
set-up times prior to the clock transition, and the synchronous inputs must be stable for a time period
equal to at least the specified minimum hold time after the clock transition.
10.9.2 Propagation Delay
There is always a time delay, known as the propagation delay, from the time instant the signal is
applied to the time the output makes the intended change. The flip-flop data sheet usually specifies
propagation delays for both HIGH-to-LOW (t pHL and for LOW-to-HIGH (t pLH output transitions.
The propagation delay is measured between 50 % points on input and output waveforms and is usually
specified for all types of input including synchronous and asynchronous inputs. The propagation delays
for LOW-to-HIGH and HIGH-to-LOW output transitions for a positive edge-triggered flip-flop are
shown in Fig. 10.44. For flip-flop 74ALS109A, t pHL and t pLH for clock input to output are respectively
18 and 16 ns. The same for the asynchronous input to output for this flip-flop are 15 and 13 ns
respectively.
399
10.9 Flip-Flop Timing Parameters
Certain timing parameters would be listed in the specification sheet of a flip-flop. Some of these
parameters, as we will see in the paragraphs to follow, are specific to the logic family to which the
flip-flop belongs. There are some parameters that have different values for different flip-flops belonging
to the same broad logic family. It is therefore important that one considers these timing parameters
before using a certain flip-flop in a given application. Some of the important ones are set-up and hold
times, propagation delay, clock pulse HIGH and LOW times, asynchronous input active pulse width,
clock transition time and maximum clock frequency.
10.9.1 Set-Up and Hold Times
The set-up time is the minimum time period for which the synchronous inputs (for example, R, S, J ,
K and DD and asynchronous inputs (for example, PRESET and CLEAR) must be stable prior to the
active clock transition for the flip-flop output to respond reliably at the clock transition. It is usually
denoted by t s (min) and is usually defined separately for synchronous and asynchronous inputs. As
an example, if in a J -K flip-flop the J and K inputs were to go to ‘1’ and ‘0’ respectively, and
if the flip-flop were negative edge triggered, the set-up time would be as shown in Fig. 10.43(a).
The set-up time in the case of 74ALS109A, which is a dual J -K positive edge-triggered flip-flop
belonging to the advanced low-power Schottky TTL logic family, is 15 ns. Also, the asynchronous
inputs, such as PRESET and CLEAR, if there, should be inactive prior to the clock transition for a
certain minimum time period if the outputs have to respond as per synchronous inputs. In the case
of 74ALS109A, the asynchronous input set-up time is 10 ns. The asynchronous input set-up time for
active low PRESET and CLEAR inputs is shown in Fig. 10.43(b), assuming a positive edge-triggered
flip-flop.
The hold time t H (min) is the minimum time period for which the synchronous inputs (R, S, J , K, DD
must remain stable in the desired logic state after the active clock transition for the flip-flop to respond
reliably. The same is depicted in Fig. 10.43(a) if the desired logic status for J and K inputs is ‘1’ and
‘0’ respectively and the flip-flop is negative edge triggered. The hold time for flip-flop 74ALS109A
is specified to be zero. To sum up, for a flip-flop to respond properly and reliably at the active clock
transition, the synchronous inputs must be stable in their intended logic states and the asynchronous
inputs must be stable in their inactive states for at least a time period equal to the specified minimum
set-up times prior to the clock transition, and the synchronous inputs must be stable for a time period
equal to at least the specified minimum hold time after the clock transition.
10.9.2 Propagation Delay
There is always a time delay, known as the propagation delay, from the time instant the signal is
applied to the time the output makes the intended change. The flip-flop data sheet usually specifies
propagation delays for both HIGH-to-LOW (t pHL and for LOW-to-HIGH (t pLH output transitions.
The propagation delay is measured between 50 % points on input and output waveforms and is usually
specified for all types of input including synchronous and asynchronous inputs. The propagation delays
for LOW-to-HIGH and HIGH-to-LOW output transitions for a positive edge-triggered flip-flop are
shown in Fig. 10.44. For flip-flop 74ALS109A, t pHL and t pLH for clock input to output are respectively
18 and 16 ns. The same for the asynchronous input to output for this flip-flop are 15 and 13 ns
respectively.