382
Digital Electronics
and negative edge triggering. The width of the narrow pulse generated by this edge detector circuit is
equal to the propagation delay of the inverter. Figure 10.25 shows the circuit symbol for the flip-flop of
Fig. 10.23 for the positive edge-triggered mode [Fig. 10.25(a)] and the negative edge-triggered mode
[Fig. 10.25(b)].
10.5 J -K Flip-Flop
A J -K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the
function table. In the case of an R-S flip-flop, the input combination S = R = 1 (in the case of a
flip-flop with active HIGH inputs) and the input combination S = R = 0 (in the case of a flip-flop
with active LOW inputs) are prohibited. In the case of a J -K flip-flop with active HIGH inputs, the
output of the flip-flop toggles, that is, it goes to the other state, for J = K = 1 . The output toggles for
J = K = 0 in the case of the flip-flop having active LOW inputs. Thus, a J -K flip-flop overcomes the
problem of a forbidden input combination of the R-S flip-flop. Figures 10.26(a) and (b) respectively
show the circuit symbol of level-triggered J -K flip-flops with active HIGH and active LOW inputs,
along with their function tables. Figure 10.27 shows the realization of a J -K flip-flop with an R-S
flip-flop.
The characteristic tables for a J -K flip-flop with active HIGH J and K inputs and a J -K flip-flop
with active LOW J and K inputs are respectively shown in Figs 10.28(a) and (b) The corresponding
Karnaugh maps are shown in Fig. 10.28(c) for the characteristics table of Fig. 10.28(a) and in Fig.
10.28(d) for the characteristic table of Fig. 10.28(b). The characteristic equations for the Karnaugh
maps of Figs 10.28(c) and (d) are respectively
Q n+1 = JJQ n + KKQ n
(10.17)
Q n+1 = JJQ n + KKQ n
(10.18)
10.5.1 J -K Flip-Flop with PRESET and CLEAR Inputs
It is often necessary to clear a flip-flop to a logic ‘0’ state (Q n = 0) or preset it to a logic ‘1’ state
(Q n = 1 ). An example of how this is realized is shown in Fig. 10.29(a). The flip-flop is cleared (that is,
Q n = 0) whenever the CLEAR input is ‘0’ and the PRESET input is ‘1’. The flip-flop is preset to the
logic ‘1’ state whenever the PRESET input is ‘0’ and the CLEAR input is ‘1’. Here, the CLEAR and
PRESET inputs are active when LOW. Figure 10.29(b) shows the circuit symbol of this presettable,
clearable, clocked J -K flip-flop. Figure 10.29(c) shows the function table of such a flip-flop. It is
evident from the function table that, whenever the PRESET input is active, the output goes to the ‘1’
state irrespective of the status of the clock, J and K inputs. Similarly, when the flip-flop is cleared, that
is, the CLEAR input is active, the output goes to the ‘0’ state irrespective of the status of the clock, J
and K inputs. In a flip-flop of this type, both PRESET and CLEAR inputs should not be made active
at the same time.
10.5.2 Master–Slave Flip-Flops
Whenever the width of the pulse clocking the flip-flop is greater than the propagation delay of the
flip-flop, the change in state at the output is not reliable. In the case of edge-triggered flip-flops, this
pulse width would be the trigger pulse width generated by the edge detector portion of the flip-flop
Digital Electronics
and negative edge triggering. The width of the narrow pulse generated by this edge detector circuit is
equal to the propagation delay of the inverter. Figure 10.25 shows the circuit symbol for the flip-flop of
Fig. 10.23 for the positive edge-triggered mode [Fig. 10.25(a)] and the negative edge-triggered mode
[Fig. 10.25(b)].
10.5 J -K Flip-Flop
A J -K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the
function table. In the case of an R-S flip-flop, the input combination S = R = 1 (in the case of a
flip-flop with active HIGH inputs) and the input combination S = R = 0 (in the case of a flip-flop
with active LOW inputs) are prohibited. In the case of a J -K flip-flop with active HIGH inputs, the
output of the flip-flop toggles, that is, it goes to the other state, for J = K = 1 . The output toggles for
J = K = 0 in the case of the flip-flop having active LOW inputs. Thus, a J -K flip-flop overcomes the
problem of a forbidden input combination of the R-S flip-flop. Figures 10.26(a) and (b) respectively
show the circuit symbol of level-triggered J -K flip-flops with active HIGH and active LOW inputs,
along with their function tables. Figure 10.27 shows the realization of a J -K flip-flop with an R-S
flip-flop.
The characteristic tables for a J -K flip-flop with active HIGH J and K inputs and a J -K flip-flop
with active LOW J and K inputs are respectively shown in Figs 10.28(a) and (b) The corresponding
Karnaugh maps are shown in Fig. 10.28(c) for the characteristics table of Fig. 10.28(a) and in Fig.
10.28(d) for the characteristic table of Fig. 10.28(b). The characteristic equations for the Karnaugh
maps of Figs 10.28(c) and (d) are respectively
Q n+1 = JJQ n + KKQ n
(10.17)
Q n+1 = JJQ n + KKQ n
(10.18)
10.5.1 J -K Flip-Flop with PRESET and CLEAR Inputs
It is often necessary to clear a flip-flop to a logic ‘0’ state (Q n = 0) or preset it to a logic ‘1’ state
(Q n = 1 ). An example of how this is realized is shown in Fig. 10.29(a). The flip-flop is cleared (that is,
Q n = 0) whenever the CLEAR input is ‘0’ and the PRESET input is ‘1’. The flip-flop is preset to the
logic ‘1’ state whenever the PRESET input is ‘0’ and the CLEAR input is ‘1’. Here, the CLEAR and
PRESET inputs are active when LOW. Figure 10.29(b) shows the circuit symbol of this presettable,
clearable, clocked J -K flip-flop. Figure 10.29(c) shows the function table of such a flip-flop. It is
evident from the function table that, whenever the PRESET input is active, the output goes to the ‘1’
state irrespective of the status of the clock, J and K inputs. Similarly, when the flip-flop is cleared, that
is, the CLEAR input is active, the output goes to the ‘0’ state irrespective of the status of the clock, J
and K inputs. In a flip-flop of this type, both PRESET and CLEAR inputs should not be made active
at the same time.
10.5.2 Master–Slave Flip-Flops
Whenever the width of the pulse clocking the flip-flop is greater than the propagation delay of the
flip-flop, the change in state at the output is not reliable. In the case of edge-triggered flip-flops, this
pulse width would be the trigger pulse width generated by the edge detector portion of the flip-flop