348
Digital Electronics
I/O (8)
I/O (8)
I (12)
I/O (8)
I/O (8)
I/O (32)
Central Switch
Matrix
34V16 PAL
I/O (8)
I/O (8)
clk (4)
I/O (8)
I/O (8)
I/O (32)
Figure 9.39 Mach-4 CPLD architecture.
performance. XC-7200 offers a logic capacity of 600–1500 gates with a speed performance of 25 ns
pin-to-pin propagation delay. XC-7300 offers a gate capacity of up to 3000 gates. Each device in the
XC-7000 family contains SPLD-like logic blocks, with each block having nine macrocells. A notable
difference between the XC-7000 family of CPLDs and their counterparts from other manufacturers is
that each macrocell has two OR gates whose outputs feed a two-bit arithmetic logic unit (ALU), which
in turn can generate any function of its two inputs. The ALU output feeds a configurable flip-flop.
The CoolRunner family of CPLDs is characterized by high speed (5 ns pin-to-pin propagation delay)
and low power consumption (100 A of standby current). The family includes the XPLAE series of
devices, available in 32, 64 and 128 macrocell versions, the XPLA2-series, which is SRAM-based and
available in 320 and 920 macrocell capacities, and the XPLA3 series, available in 32, 64, 128, 256
and 384 macrocell versions.
The XC-9500 family of devices comprises the XC-9536, XC-9572, XC-95108, XC-95144, XC95216 and XC-95288 series of CPLDs. The family offers a logic capacity ranging from 800 gates (in
the case of XC-9536) to 6400 gates (in the case of XC-95288), with a propagation delay varying from 5
ns (in the case of XC-9536) to 15 ns (in the case of XC-95288). Architectural features of the XC-9500
family of CPLDs provide in-system programmability with a minimum of 10 000 program/erase cycles.
Other features include output slew rate control and user-programmable ground pins, which help reduce
system noise.
Digital Electronics
I/O (8)
I/O (8)
I (12)
I/O (8)
I/O (8)
I/O (32)
Central Switch
Matrix
34V16 PAL
I/O (8)
I/O (8)
clk (4)
I/O (8)
I/O (8)
I/O (32)
Figure 9.39 Mach-4 CPLD architecture.
performance. XC-7200 offers a logic capacity of 600–1500 gates with a speed performance of 25 ns
pin-to-pin propagation delay. XC-7300 offers a gate capacity of up to 3000 gates. Each device in the
XC-7000 family contains SPLD-like logic blocks, with each block having nine macrocells. A notable
difference between the XC-7000 family of CPLDs and their counterparts from other manufacturers is
that each macrocell has two OR gates whose outputs feed a two-bit arithmetic logic unit (ALU), which
in turn can generate any function of its two inputs. The ALU output feeds a configurable flip-flop.
The CoolRunner family of CPLDs is characterized by high speed (5 ns pin-to-pin propagation delay)
and low power consumption (100 A of standby current). The family includes the XPLAE series of
devices, available in 32, 64 and 128 macrocell versions, the XPLA2-series, which is SRAM-based and
available in 320 and 920 macrocell capacities, and the XPLA3 series, available in 32, 64, 128, 256
and 384 macrocell versions.
The XC-9500 family of devices comprises the XC-9536, XC-9572, XC-95108, XC-95144, XC95216 and XC-95288 series of CPLDs. The family offers a logic capacity ranging from 800 gates (in
the case of XC-9536) to 6400 gates (in the case of XC-95288), with a propagation delay varying from 5
ns (in the case of XC-9536) to 15 ns (in the case of XC-95288). Architectural features of the XC-9500
family of CPLDs provide in-system programmability with a minimum of 10 000 program/erase cycles.
Other features include output slew rate control and user-programmable ground pins, which help reduce
system noise.