346
Digital Electronics
4 to 1
MUX
D
Q
Q
2 to 1
MUX
AR
SP
CLK
Figure 9.37 Architecture of an output GAL 22V10 logic macrocell.
Figure 9.39 shows the basic architecture of Mach-4 CPLDs. The number of 34V16-like PALs
used varies from 6 to 16. Each 34V16-like PAL block consists of a maximum of 34 inputs and
16 outputs. The 34 inputs include 16 outputs that are fed back. All connections in the case of
Mach-4 CPLDs, from one PAL block to another and also from a PAL block back to itself, are
routed through a central switching matrix, on account of which all connections travel through the
same path. This feature gives more predictable time delays in circuits implemented on Mach-4
devices.
Lattice offers the pLSI and ispLSI 1000-series, 2000-series and 3000-series of CPLDs. ispLSI
devices are similar to pLSI devices except that they are in-system programmable. The three series
of devices differ mainly in logic capacities and speed performance. The logic capacity in the case of
the 1000-series CPLDs ranges from about 1200 to 4000 gates, and the pin-to-pin propagation delay
is of the order of 10 ns. The ispLSI-1016 CPLD is one such device from the 1000-series of devices.
It has a logic capacity of 2000 PLD gates and a pin-to-pin propagation delay of 7.5 ns. The device
has four dedicated inputs, 32 universal I/O pins and 96 registers. It uses high-performance E
2 CMOS
technology, because of which it offers reprogrammability of the logic as well as the interconnects to
provide truly reconfigurable systems.
The 2000-series devices have a logic capacity of 600–2000 equivalent gates that offer a higher ratio
of macrocells to I/O pins. With a pin-to-pin propagation delay of 5.5 ns, they offer a higher speed
performance compared with 1000-series devices. Of the three device families, the 3000-series has the
highest logic capacity (up to 5000 equivalent gates). The propagation delay is in the range 10–15 ns.
The 3000-series of devices offers some enhancements over the other two series of CPLDs to support
more recent design approaches.
Digital Electronics
4 to 1
MUX
D
Q
Q
2 to 1
MUX
AR
SP
CLK
Figure 9.37 Architecture of an output GAL 22V10 logic macrocell.
Figure 9.39 shows the basic architecture of Mach-4 CPLDs. The number of 34V16-like PALs
used varies from 6 to 16. Each 34V16-like PAL block consists of a maximum of 34 inputs and
16 outputs. The 34 inputs include 16 outputs that are fed back. All connections in the case of
Mach-4 CPLDs, from one PAL block to another and also from a PAL block back to itself, are
routed through a central switching matrix, on account of which all connections travel through the
same path. This feature gives more predictable time delays in circuits implemented on Mach-4
devices.
Lattice offers the pLSI and ispLSI 1000-series, 2000-series and 3000-series of CPLDs. ispLSI
devices are similar to pLSI devices except that they are in-system programmable. The three series
of devices differ mainly in logic capacities and speed performance. The logic capacity in the case of
the 1000-series CPLDs ranges from about 1200 to 4000 gates, and the pin-to-pin propagation delay
is of the order of 10 ns. The ispLSI-1016 CPLD is one such device from the 1000-series of devices.
It has a logic capacity of 2000 PLD gates and a pin-to-pin propagation delay of 7.5 ns. The device
has four dedicated inputs, 32 universal I/O pins and 96 registers. It uses high-performance E
2 CMOS
technology, because of which it offers reprogrammability of the logic as well as the interconnects to
provide truly reconfigurable systems.
The 2000-series devices have a logic capacity of 600–2000 equivalent gates that offer a higher ratio
of macrocells to I/O pins. With a pin-to-pin propagation delay of 5.5 ns, they offer a higher speed
performance compared with 1000-series devices. Of the three device families, the 3000-series has the
highest logic capacity (up to 5000 equivalent gates). The propagation delay is in the range 10–15 ns.
The 3000-series of devices offers some enhancements over the other two series of CPLDs to support
more recent design approaches.