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Digital Electronics
(k)
AND-Gates
(Product terms)
(m)
OR-Gates
(Sum terms)
Inputs(n)
Output(m)
Figure 9.13 Generalized representation of PLA architecture.
each of the Boolean functions and their complements should be simplified. What is desirable is to have
fewer product terms and product terms that are common to other functions. We would recall that PLAs
offer the flexibility of implementing Boolean functions in both AND-OR and AND-OR-INVERT forms.
Example 9.2
Show the logic arrangement of both a PROM and a PLA required to implement a binary full adder.
Solution
The truth table of a full adder is given in Table 9.1. The Boolean expressions for sum S and carry-out
C o can be written as follows:
S = 1 2 4 7
(9.3)
C o = 3 5 6 7
(9.4)
Figure 9.14 shows the implementation with an 8 × 2 PROM.
If we simplify the Boolean expressions for the sum and carry outputs, we will find that the expression
for the sum output cannot be simplified any further, and also that the expression for carry-out can be
simplified to three product terms with fewer literals. If we examine even the existing expressions, we
find that we would need seven AND gates in the PLA implementation. And if we use the simplified
expressions, even then we would require the same number of AND gates. Therefore, the simplification
here would not help as far as its implementation with a PLA is concerned. Figure 9.15 shows the
implementation of a full adder with a PLA device.
Table 9.1 Truth table for example 9.2.
A
B
Carry-in
Sum
Carry-out
(C i )
(S)
(C o )
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1