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Digital Electronics
a GAL device can be erased and reprogrammed. Also, it has reprogrammable output logic.
This feature makes it particularly attractive at the device prototyping stage, as any bugs in
the logic can be corrected by reprogramming. A similar device called PEEL (Programmable
Electrically Erasable Logic) was introduced by the International CMOS Technology (ICT)
Corporation.
9.2.5 Complex Programmable Logic Device
Programmable logic devices such as PLAs, PALs, GALs and other PAL-like devices are often grouped
into a single category called simple programmable logic devices (SPLDs) to distinguish them from the
ones that are far more complex. A complex programmable logic device (CPLD), as the name suggests,
is a much more complex device than any of the programmable logic devices discussed so far. A CPLD
may contain circuitry equivalent to that of several PAL devices linked to each other by programmable
interconnections. Figure 9.6 shows the internal structure of a typical CPLD. Each of the four logic
blocks is equivalent to a PLD such as a PAL device. The number of logic blocks in a CPLD could be
more or less than four. Each of the logic blocks has programmable interconnections. A switch matrix
is used for logic block to logic block interconnections. Also, the switch matrix in a CPLD may or
may not be fully connected. That is, some of the possible connections between logic block outputs and
inputs may not be supported by a given CPLD. While the complexity of a typical PAL device may
be of the order of a few hundred logic gates, a CPLD may have a complexity equivalent to tens of
thousands of logic gates. When compared with FPGAs, CPLDs offer predictable timing characteristics
owing to their less flexible internal architecture and are thus ideal for critical control applications and
other applications where a high performance level is required. Also, because of their relatively much
lower power consumption and lower cost, CPLDs are an ideal solution for battery-operated portable
applications such as mobile phones, digital assistants and so on. A CPLD can be programmed either
by using a PAL programmer or by feeding it with a serial data stream from a PC after soldering it on
the PC board. A circuit on the CPLD decodes the data stream and configures it to perform the intended
logic function.
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Switch Matrix
Figure 9.6 CPLD architecture.
Digital Electronics
a GAL device can be erased and reprogrammed. Also, it has reprogrammable output logic.
This feature makes it particularly attractive at the device prototyping stage, as any bugs in
the logic can be corrected by reprogramming. A similar device called PEEL (Programmable
Electrically Erasable Logic) was introduced by the International CMOS Technology (ICT)
Corporation.
9.2.5 Complex Programmable Logic Device
Programmable logic devices such as PLAs, PALs, GALs and other PAL-like devices are often grouped
into a single category called simple programmable logic devices (SPLDs) to distinguish them from the
ones that are far more complex. A complex programmable logic device (CPLD), as the name suggests,
is a much more complex device than any of the programmable logic devices discussed so far. A CPLD
may contain circuitry equivalent to that of several PAL devices linked to each other by programmable
interconnections. Figure 9.6 shows the internal structure of a typical CPLD. Each of the four logic
blocks is equivalent to a PLD such as a PAL device. The number of logic blocks in a CPLD could be
more or less than four. Each of the logic blocks has programmable interconnections. A switch matrix
is used for logic block to logic block interconnections. Also, the switch matrix in a CPLD may or
may not be fully connected. That is, some of the possible connections between logic block outputs and
inputs may not be supported by a given CPLD. While the complexity of a typical PAL device may
be of the order of a few hundred logic gates, a CPLD may have a complexity equivalent to tens of
thousands of logic gates. When compared with FPGAs, CPLDs offer predictable timing characteristics
owing to their less flexible internal architecture and are thus ideal for critical control applications and
other applications where a high performance level is required. Also, because of their relatively much
lower power consumption and lower cost, CPLDs are an ideal solution for battery-operated portable
applications such as mobile phones, digital assistants and so on. A CPLD can be programmed either
by using a PAL programmer or by feeding it with a serial data stream from a PC after soldering it on
the PC board. A circuit on the CPLD decodes the data stream and configures it to perform the intended
logic function.
Logic
Block
Logic
Block
Logic
Block
Logic
Block
Switch Matrix
Figure 9.6 CPLD architecture.