256
Digital Electronics
otherwise have resulted from some previous operation. In order to explain the concept, let us define
two new binary variables: P i called CARRY PROPAGATE and G i called CARRY GENERATE.
Binary variable G i is so called as it generates a carry whenever A i and B i are ‘1’. Binary variable
P i is called CARRY PROPAGATE as it is instrumental in propagation of C i to C i+1 . CARRY,
SUM, CARRY GENERATE and CARRY PROPAGATE parameters are given by the following
expressions:
P i = A i ⊕ B i
(7.18)
G i = A i B i
(7.19)
S i = P i ⊕ C i
(7.20)
C i+1 = P i C i + G i
(7.21)
In the next step, we write Boolean expressions for the CARRY output of each full adder stage in the
four-bit binary adder. We obtain the following expressions:
C 2 = G 1 + P 1 C 1
(7.22)
C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 1 C 1 = G 2 + P 2 G 1 + P 1 P 2 C 1
(7.23)
C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 2 G 1 + P 1 P 2 C 1
C 4 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 1 P 2 P 3 C 1
(7.24)
From the expressions for C 2 , C 3 and C 4 it is clear that C 4 need not wait for C 3 and C 2 to propagate.
Similarly, C 3 does not wait for C 2 to propagate. Hardware implementation of these expressions gives
us a kind of look-ahead carry generator. A look-ahead carry generator that implements the above
expressions using AND-OR logic is shown in Fig. 7.31.
Figure 7.32 shows the four-bit adder with the look-ahead carry concept incorporated. The block
labelled look-ahead carry generator is similar to that shown in Fig. 7.31. The logic gates shown to the
left of the block represent the input half-adder portion of various full adders constituting the four-bit
adder. The EX-OR gates shown on the right are a portion of the output half-adders of various full
adders.
All sum outputs in this case will be available at the output after a delay of two levels of logic
gates. 74182 is a typical look-ahead carry generator IC of the TTL logic family. This IC can be
used to generate relevant carry inputs for four four-bit binary adders connected in cascade to perform
operation on two 16-bit numbers. Of course, the four-bit adders should be of the type so as to produce
CARRY GENERATE and CARRY PROPAGATE outputs. Figure 7.33 shows the arrangement. In
the figure shown, C n is the CARRY input, G 0 , G 1 , G 2 and G 3 are CARRY GENERATE inputs
for 74182 and P 0 , P 1 , P 2 and P 3 are CARRY PROPAGATE inputs for 74182. C n+x , C n+y and
C n+z are the CARRY outputs generated by 74182 for the four-bit adders. The G and P outputs
of 74182 need to be cascaded. Figure 7.34 shows the arrangement needed for adding two 64-bit
numbers.
Digital Electronics
otherwise have resulted from some previous operation. In order to explain the concept, let us define
two new binary variables: P i called CARRY PROPAGATE and G i called CARRY GENERATE.
Binary variable G i is so called as it generates a carry whenever A i and B i are ‘1’. Binary variable
P i is called CARRY PROPAGATE as it is instrumental in propagation of C i to C i+1 . CARRY,
SUM, CARRY GENERATE and CARRY PROPAGATE parameters are given by the following
expressions:
P i = A i ⊕ B i
(7.18)
G i = A i B i
(7.19)
S i = P i ⊕ C i
(7.20)
C i+1 = P i C i + G i
(7.21)
In the next step, we write Boolean expressions for the CARRY output of each full adder stage in the
four-bit binary adder. We obtain the following expressions:
C 2 = G 1 + P 1 C 1
(7.22)
C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 1 C 1 = G 2 + P 2 G 1 + P 1 P 2 C 1
(7.23)
C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 2 G 1 + P 1 P 2 C 1
C 4 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 1 P 2 P 3 C 1
(7.24)
From the expressions for C 2 , C 3 and C 4 it is clear that C 4 need not wait for C 3 and C 2 to propagate.
Similarly, C 3 does not wait for C 2 to propagate. Hardware implementation of these expressions gives
us a kind of look-ahead carry generator. A look-ahead carry generator that implements the above
expressions using AND-OR logic is shown in Fig. 7.31.
Figure 7.32 shows the four-bit adder with the look-ahead carry concept incorporated. The block
labelled look-ahead carry generator is similar to that shown in Fig. 7.31. The logic gates shown to the
left of the block represent the input half-adder portion of various full adders constituting the four-bit
adder. The EX-OR gates shown on the right are a portion of the output half-adders of various full
adders.
All sum outputs in this case will be available at the output after a delay of two levels of logic
gates. 74182 is a typical look-ahead carry generator IC of the TTL logic family. This IC can be
used to generate relevant carry inputs for four four-bit binary adders connected in cascade to perform
operation on two 16-bit numbers. Of course, the four-bit adders should be of the type so as to produce
CARRY GENERATE and CARRY PROPAGATE outputs. Figure 7.33 shows the arrangement. In
the figure shown, C n is the CARRY input, G 0 , G 1 , G 2 and G 3 are CARRY GENERATE inputs
for 74182 and P 0 , P 1 , P 2 and P 3 are CARRY PROPAGATE inputs for 74182. C n+x , C n+y and
C n+z are the CARRY outputs generated by 74182 for the four-bit adders. The G and P outputs
of 74182 need to be cascaded. Figure 7.34 shows the arrangement needed for adding two 64-bit
numbers.