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Digital Electronics
5.5.2.4 74AC/ACT Series
The 74AC series is presently the fastest CMOS logic family. This logic family has the best
combination of high speed, low power consumption and high output drive capability. Again, 74ACT
is only a process variation of 74AC. In addition, 74ACT series devices have TTL-compatible
inputs.
The characteristic parameters of the 74C/74HC/74HCT/74AC/74ACT series CMOS are summarized
as follows (for V DD = 5 V): V IH (min.) = 3.5 V (74C), 3.5 V (74HC and 74AC) and 2.0 V (74HCT and
74ACT); V OH (min.) = 4.5 V (74C) and 4.9 V (74HC, 74HCT, 74AC and 74ACT); V IL (max.) = 1.5 V
(74C), 1.0 V (74HC), 0.8 V (74HCT), 1.5 V (74AC) and 0.8 V (74ACT); V OL (max.) = 0.5 V (74C) and
0.1 V (74HC, 74HCT, 74AC and 74ACT); I IH (max.) = 1 A; I IL (max.) = 1 A; I OH (max.) = 0.4 mA
(74C), 4.0 mA (74HC and 74HCT) and 24 mA (74AC and 74ACT); I OL (max.) = 0.4 mA (74C), 4.0 mA
(74HC and 74HCT) and 24 mA (74AC and 74ACT); V NH = 1.4 V (74C, 74HC and 74AC) and 2.9 V
(74HCT and 74ACT); V NL = 1.4 V (74C), 0.9 V (74HC), 0.7 V (74HCT and 74ACT) and 1.4 V (74AC);
propagation delay = 50 ns (74C), 8 ns (74HC and 74HCT) and 4.7 ns (74AC and 74ACT); power
dissipation per gate (for f = 100 kHz) = 0.1 mW (74C), 0.17 mW (74HC and 74HCT) and 0.08 mW
(74AC and 74ACT); speed–power product (for f = 100 kHz) = 5 pJ (74C), 1.4 pJ (74HC and 74HCT)
and 0.37 pJ (74AC and 74ACT); maximum flip-flop toggle rate = 12 MHz (74C), 40 MHz (74HC and
74HCT) and 100 MHz (74AC and 74ACT).
Example 5.7
Draw the internal schematic of: (a) a two-wide, four-input AND-OR-INVERT logic function in CMOS
and (b) a two-wide, four-input OR-AND-INVERT logic function in CMOS.
Solution
(a) Let us assume that A, B, C, D, E, F , G and H are the logic variables. The output Y of this logic
function can then be expressed by the equation
Y = AABBCCD + EEFFGGHH
(5.5)
Following the principles explained earlier in the text, the internal schematic is shown in Fig. 5.53(a).
Series connection of N-channel MOSFETs on the left simulates ANDing of A, B, C and D,
whereas series connection of N-channel MOSFETs on the right simulates ANDing of E, F , G
and H. Parallel connection of two branches produces ORing of the ANDed outputs. Since the
P-channel MOSFET arrangement is the complement of the N-channel MOSFET arrangement, the
final output is what is given by Equation (5.5).
(b) The output Y of this logic function can be expressed by the equation
Y = A + B + C + DDDDE + F + G + HH
(5.6)
Figure 5.53(b) shows the internal schematic, which can be explained on similar lines.
Example 5.8
Determine the logic function performed by the CMOS digital circuit of Fig. 5.54.
Digital Electronics
5.5.2.4 74AC/ACT Series
The 74AC series is presently the fastest CMOS logic family. This logic family has the best
combination of high speed, low power consumption and high output drive capability. Again, 74ACT
is only a process variation of 74AC. In addition, 74ACT series devices have TTL-compatible
inputs.
The characteristic parameters of the 74C/74HC/74HCT/74AC/74ACT series CMOS are summarized
as follows (for V DD = 5 V): V IH (min.) = 3.5 V (74C), 3.5 V (74HC and 74AC) and 2.0 V (74HCT and
74ACT); V OH (min.) = 4.5 V (74C) and 4.9 V (74HC, 74HCT, 74AC and 74ACT); V IL (max.) = 1.5 V
(74C), 1.0 V (74HC), 0.8 V (74HCT), 1.5 V (74AC) and 0.8 V (74ACT); V OL (max.) = 0.5 V (74C) and
0.1 V (74HC, 74HCT, 74AC and 74ACT); I IH (max.) = 1 A; I IL (max.) = 1 A; I OH (max.) = 0.4 mA
(74C), 4.0 mA (74HC and 74HCT) and 24 mA (74AC and 74ACT); I OL (max.) = 0.4 mA (74C), 4.0 mA
(74HC and 74HCT) and 24 mA (74AC and 74ACT); V NH = 1.4 V (74C, 74HC and 74AC) and 2.9 V
(74HCT and 74ACT); V NL = 1.4 V (74C), 0.9 V (74HC), 0.7 V (74HCT and 74ACT) and 1.4 V (74AC);
propagation delay = 50 ns (74C), 8 ns (74HC and 74HCT) and 4.7 ns (74AC and 74ACT); power
dissipation per gate (for f = 100 kHz) = 0.1 mW (74C), 0.17 mW (74HC and 74HCT) and 0.08 mW
(74AC and 74ACT); speed–power product (for f = 100 kHz) = 5 pJ (74C), 1.4 pJ (74HC and 74HCT)
and 0.37 pJ (74AC and 74ACT); maximum flip-flop toggle rate = 12 MHz (74C), 40 MHz (74HC and
74HCT) and 100 MHz (74AC and 74ACT).
Example 5.7
Draw the internal schematic of: (a) a two-wide, four-input AND-OR-INVERT logic function in CMOS
and (b) a two-wide, four-input OR-AND-INVERT logic function in CMOS.
Solution
(a) Let us assume that A, B, C, D, E, F , G and H are the logic variables. The output Y of this logic
function can then be expressed by the equation
Y = AABBCCD + EEFFGGHH
(5.5)
Following the principles explained earlier in the text, the internal schematic is shown in Fig. 5.53(a).
Series connection of N-channel MOSFETs on the left simulates ANDing of A, B, C and D,
whereas series connection of N-channel MOSFETs on the right simulates ANDing of E, F , G
and H. Parallel connection of two branches produces ORing of the ANDed outputs. Since the
P-channel MOSFET arrangement is the complement of the N-channel MOSFET arrangement, the
final output is what is given by Equation (5.5).
(b) The output Y of this logic function can be expressed by the equation
Y = A + B + C + DDDDE + F + G + HH
(5.6)
Figure 5.53(b) shows the internal schematic, which can be explained on similar lines.
Example 5.8
Determine the logic function performed by the CMOS digital circuit of Fig. 5.54.