Logic Families
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a totem-pole connection is that it offers low-output impedance in both the HIGH and LOW output
states. In the HIGH state, Q 3 acts as an emitter follower and has an output impedance of about 70 .
In the LOW state, Q 4 is saturated and the output impedance is approximately 10 . Because of the
low output impedance, any stray capacitance at the output can be charged or discharged very rapidly
through this low impedance, thus allowing quick transitions at the output from one state to the other.
Another advantage is that, when the output is in the logic LOW state, transistor Q 4 would need to
conduct a fairly large current if its collector were tied to V CC through R 3 only. A nonconducting
Q 3 overcomes this problem. A disadvantage of the totem-pole output configuration results from the
switch-off action of Q 4 being slower than the switch-on action of Q 3 . On account of this, there will be
a small fraction of time, of the order of a few nanoseconds, when both the transistors are conducting,
thus drawing heavy current from the supply.
5.3.1.3 Characteristic Features
To sum up, the characteristic parameters and features of the standard TTL family of devices
include the following: V IL = 0.8 V; V IH = 2 V; I IH = 40 A; I IL = 1.6 mA; V OH = 2.4 V; V OL = 0.4 V;
I OH = 400 A; I OL = 16 mA; V CC = 4.75–5.25 V (74-series) and 4.5–5.5 V (54-series); propagation
delay (for a load resistance of 400 , a load capacitance of 15 pF and an ambient temperature
of 25 °C) = 22 ns (max.) for LOW-to-HIGH transition at the output and 15 ns (max.) for HIGHto-LOW output transition; worst-case noise margin = 0.4 V; fan-out = 10; I CCH (for all four
gates) = 8 mA; I CCL (for all four gates) = 22 mA; operating temperature range = 0–70 °C (74series) and −55 to +125 °C (54-series); speed–power product = 100 pJ; maximum flip-flop toggle
frequency = 35 MHz.
5.3.2 Other Logic Gates in Standard TTL
As outlined earlier, the NAND gate is the fundamental building block of the TTL family. In the
following paragraphs we will look at the internal schematics of the other logic gates and find for
ourselves their similarity to the schematic of the NAND gate discussed in detail in earlier paragraphs.
5.3.2.1 NOT Gate (or Inverter)
Figure 5.8 shows the internal schematic of a NOT gate (inverter) in the standard TTL family. The
schematic shown is that of one of the six inverters in a hex inverter (type 7404/5404). The internal
schematic is just the same as that of the NAND gate except that the input transistor is a normal single
emitter NPN transistor instead of a multi-emitter one. The circuit is self-explanatory.
5.3.2.2 NOR Gate
Figure 5.9 shows the internal schematic of a NOR gate in the standard TTL family. The schematic
shown is that of one of the four NOR gates in a quad two-input NOR gate (type 7402/5402). On the
input side there are two separate transistors instead of the multi-emitter transistor of the NAND gate.
The inputs are fed to the emitters of the two transistors, the collectors of which again feed the bases of
the two transistors with their collector and emitter terminals tied together. The resistance values used
are the same as those used in the case of the NAND gate. The output stage is also the same totem-pole
output stage. The circuit is self-explanatory. The only input condition for which transistors Q 3 and Q 4
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a totem-pole connection is that it offers low-output impedance in both the HIGH and LOW output
states. In the HIGH state, Q 3 acts as an emitter follower and has an output impedance of about 70 .
In the LOW state, Q 4 is saturated and the output impedance is approximately 10 . Because of the
low output impedance, any stray capacitance at the output can be charged or discharged very rapidly
through this low impedance, thus allowing quick transitions at the output from one state to the other.
Another advantage is that, when the output is in the logic LOW state, transistor Q 4 would need to
conduct a fairly large current if its collector were tied to V CC through R 3 only. A nonconducting
Q 3 overcomes this problem. A disadvantage of the totem-pole output configuration results from the
switch-off action of Q 4 being slower than the switch-on action of Q 3 . On account of this, there will be
a small fraction of time, of the order of a few nanoseconds, when both the transistors are conducting,
thus drawing heavy current from the supply.
5.3.1.3 Characteristic Features
To sum up, the characteristic parameters and features of the standard TTL family of devices
include the following: V IL = 0.8 V; V IH = 2 V; I IH = 40 A; I IL = 1.6 mA; V OH = 2.4 V; V OL = 0.4 V;
I OH = 400 A; I OL = 16 mA; V CC = 4.75–5.25 V (74-series) and 4.5–5.5 V (54-series); propagation
delay (for a load resistance of 400 , a load capacitance of 15 pF and an ambient temperature
of 25 °C) = 22 ns (max.) for LOW-to-HIGH transition at the output and 15 ns (max.) for HIGHto-LOW output transition; worst-case noise margin = 0.4 V; fan-out = 10; I CCH (for all four
gates) = 8 mA; I CCL (for all four gates) = 22 mA; operating temperature range = 0–70 °C (74series) and −55 to +125 °C (54-series); speed–power product = 100 pJ; maximum flip-flop toggle
frequency = 35 MHz.
5.3.2 Other Logic Gates in Standard TTL
As outlined earlier, the NAND gate is the fundamental building block of the TTL family. In the
following paragraphs we will look at the internal schematics of the other logic gates and find for
ourselves their similarity to the schematic of the NAND gate discussed in detail in earlier paragraphs.
5.3.2.1 NOT Gate (or Inverter)
Figure 5.8 shows the internal schematic of a NOT gate (inverter) in the standard TTL family. The
schematic shown is that of one of the six inverters in a hex inverter (type 7404/5404). The internal
schematic is just the same as that of the NAND gate except that the input transistor is a normal single
emitter NPN transistor instead of a multi-emitter one. The circuit is self-explanatory.
5.3.2.2 NOR Gate
Figure 5.9 shows the internal schematic of a NOR gate in the standard TTL family. The schematic
shown is that of one of the four NOR gates in a quad two-input NOR gate (type 7402/5402). On the
input side there are two separate transistors instead of the multi-emitter transistor of the NAND gate.
The inputs are fed to the emitters of the two transistors, the collectors of which again feed the bases of
the two transistors with their collector and emitter terminals tied together. The resistance values used
are the same as those used in the case of the NAND gate. The output stage is also the same totem-pole
output stage. The circuit is self-explanatory. The only input condition for which transistors Q 3 and Q 4