5.4 Evaluation Result
We implemented signal processing functions of the infrared image sensor of
AKATSUKI onto one FPGA chip with NanoBridge
® using the architecture
described in preceding sections. The original digital electronics is shown in
Fig. 16. Its signal processor consists of one central processing unit (CPU) board
with a Japan Aerospace Exploration Agency (JAXA) authorized 64bit microprocessor HR5000 and one FPGA board with two Microsemi RTSX72SU FPGAs. Several
dedicated operations for an infrared image detector were implemented. They are
superposition, mean, median, and normalize functions to improve intensity. These
functions were provided for the purpose of the evaluation of functions themselves.
These functions were evaluated onboard to see which was the most effective for
compensating dispersion of detector pixels.
The functions were implemented in the signal processing unit of AKATSUKI
with two modules as described above, and we had a software model of the functions
for these modules. The software model corresponded to the structure of one MCU
and two FPGAs. We rearrange the structures of functions in accordance with the
GPE architecture, which are described in preceding sections and transported the
functions on one NanoBridge
® FPGA using CWB. These functions have successfully been implemented in one NanoBridge
® FPGA. A dedicated arithmetic and
logic unit (ALU) was implemented in accordance with step 2 of the design flow of
GPE architecture described in the preceding section as shown in Fig. 17. The
overview of the test set is shown in Fig. 18.
The maximum power consumption of the original signal processor was estimated
as 7.4 W, and it included margin. The nominal power consumption of the original
signal processor was estimated as 4.9 W in accordance with the measured value of
the whole electronics unit. As for the FPGA implementation, the nominal power
consumption of one FPGA used in the original signal processor was estimated as
Fig. 14 Cu bridge
formulation in NanoBridge
®
[26]
52
H. Hihara et al.
We implemented signal processing functions of the infrared image sensor of
AKATSUKI onto one FPGA chip with NanoBridge
® using the architecture
described in preceding sections. The original digital electronics is shown in
Fig. 16. Its signal processor consists of one central processing unit (CPU) board
with a Japan Aerospace Exploration Agency (JAXA) authorized 64bit microprocessor HR5000 and one FPGA board with two Microsemi RTSX72SU FPGAs. Several
dedicated operations for an infrared image detector were implemented. They are
superposition, mean, median, and normalize functions to improve intensity. These
functions were provided for the purpose of the evaluation of functions themselves.
These functions were evaluated onboard to see which was the most effective for
compensating dispersion of detector pixels.
The functions were implemented in the signal processing unit of AKATSUKI
with two modules as described above, and we had a software model of the functions
for these modules. The software model corresponded to the structure of one MCU
and two FPGAs. We rearrange the structures of functions in accordance with the
GPE architecture, which are described in preceding sections and transported the
functions on one NanoBridge
® FPGA using CWB. These functions have successfully been implemented in one NanoBridge
® FPGA. A dedicated arithmetic and
logic unit (ALU) was implemented in accordance with step 2 of the design flow of
GPE architecture described in the preceding section as shown in Fig. 17. The
overview of the test set is shown in Fig. 18.
The maximum power consumption of the original signal processor was estimated
as 7.4 W, and it included margin. The nominal power consumption of the original
signal processor was estimated as 4.9 W in accordance with the measured value of
the whole electronics unit. As for the FPGA implementation, the nominal power
consumption of one FPGA used in the original signal processor was estimated as
Fig. 14 Cu bridge
formulation in NanoBridge
®
[26]
52
H. Hihara et al.