representations of high-level programming languages using a high-level synthesis
tool like CWB. Finite state transitions and data paths between function blocks are also
defined in the design flow through high-level synthesis in accordance with the context
of an application. Inputs and Outputs are defined in HDL in step 4 through behavioral
synthesis, and they correspond to the bottom layer of GPE architecture. Dotted lines
show state transitions and solid lines show data paths in Fig. 11.
The implementation example has already been demonstrated in our previous
work [25]. We implemented signal processing functions of the infrared image sensor
of AKATSUKI onto one atomic switch FPGA [26] to evaluate GPE architecture and
the design flow. The result showed remarkable power consumption reduction as
shown in the next section.
Dependability design is also required in accordance with each layer of GPE
architecture. We proposed dependability implementation scheme for GPE architecture [16]. Atomic switches can be used for the implementation design in Switch
layer, Coarse grained layer, and Fine grained layer as shown in Table 1.
f(x)
g(x)
h(x)
Synthesize the dedicated
functions as operators
Primitives of FPGA/ASIC
Define contexts and
state transitions
f(x)
g(x)
h(x)
Fig. 11 Design process
Table 1 Atomic switch application for each GPE architecture layer
Layer
Implementation
Remarks
Switch
layer
Routing by open standards, ex. SpaceWire [27] Routing switches with atomic
switches
Coarse
grained
layer
Comparison decision using triple modular
redundancy (TMR) [3, 4], CRAFTSYSTEM
[28, 29], Software communication [30], etc.
Coarse grained connections with
atomic switches
Fine
grained
layer
TMR with a voter, etc.
Atomic switch connections using
the framework of robust fabric
[3, 4, 16, 31]
48
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