7.2 Patterning and Assembly
215
In contrast to optical confinement, electronic confinement takes place on the
nanoscale. Thus, quantum structures inscribed top-down (instead of bottom-up by
growth) can only fulfil their role if length scales comparable to the electronic particle’s de-Broglie wavelength are patterned. Moreover, in order to achieve denser and
denser transistor packaging on integrated circuits, transistor structures are further and
further miniaturised, until the natural limitations imposed by quantum tunnelling are
reached on the electronic side or the processing precision is exhausted on the lithography and etching side. While mass production of integrated-circuit chips requires a
parallel, scalable process such as photolithography, it also faces resolution limitations
imposed by the optical wavelength employed for lithography.
An alternative lithography technique uses processing precision is exhausted
directed onto the sample for serial position-after-position development of a defined
pattern into the resist. Its working principle is based on that of a scanning electron
microscope, which rasters the resist with a focused electron beam. While the precision can reach well below the microscale down to the lower nanoscale, the speed of
inscribing the pattern is very low. Thus, this time-costly method is mainly attractive
for lab-scale research purposes and remains an indispensable tool for nanostructuring
facilities.
Once the pattern is defined and developed, the residue is rinsed off to provide the
mask. The exposed facet of the sample material can then for instance be etched or
metallised. Different etching techniques result in different structuring qualities, as
can be seen for the examples of micropillar etchings based on wet-chemical etching,
plasma or reactive-ion etching discussed for instance in [20, 21]. It should be noted
that etching rates can be different for different materials and crystal orientations,
and that the aspect ratio, shape and amount of underetching strongly depend on the
combination of etch, sample and exposure time. The interested reader is referred to
textbooks on processing techniques, e.g. [22].
More straight forward is the metallisation process of a masked sample. Either a
patterned resist is used, which is lifted off after metal deposition (e.g. by physical
vapour deposition or sputtering), or by a shadow mask, which is placed on top of
the sample and exposes the desired sample region to the deposition of metal. In both
cases, removal of the mask leaves behind the metallised areas and the previouslyprotected non-metallised surfaces.
For high-precision contacting schemes, typically lithography steps are involved,
which require homogeneous plane deposition of (polymer) resist material, development of the resist, setting free of facets for metallisation, and rinsing of the residues
after the whole process. Indeed, this is the preferred method for device fabrication
with high-precision contacts, and widely used for 2D-materials optoelectronic device
preparation.
In (nowadays rather rare) situations, where no micron or sub-micron precision
is needed, coarse masking with a shadow mask remains an option. A shadow mask
can be produced for instance by laser cutting from a ten-micrometer thin sheet of
aluminium foil. In [23], such shadow mask has been used to deposit a sequence of
20 nm titanium and 200 nm gold as films on top of each other to form electric contacts
on graphene, to give an example (see Fig. 7.3). However, with this approach, electrode
gaps on the order of 30 to 40 nm pose a lower limit.
215
In contrast to optical confinement, electronic confinement takes place on the
nanoscale. Thus, quantum structures inscribed top-down (instead of bottom-up by
growth) can only fulfil their role if length scales comparable to the electronic particle’s de-Broglie wavelength are patterned. Moreover, in order to achieve denser and
denser transistor packaging on integrated circuits, transistor structures are further and
further miniaturised, until the natural limitations imposed by quantum tunnelling are
reached on the electronic side or the processing precision is exhausted on the lithography and etching side. While mass production of integrated-circuit chips requires a
parallel, scalable process such as photolithography, it also faces resolution limitations
imposed by the optical wavelength employed for lithography.
An alternative lithography technique uses processing precision is exhausted
directed onto the sample for serial position-after-position development of a defined
pattern into the resist. Its working principle is based on that of a scanning electron
microscope, which rasters the resist with a focused electron beam. While the precision can reach well below the microscale down to the lower nanoscale, the speed of
inscribing the pattern is very low. Thus, this time-costly method is mainly attractive
for lab-scale research purposes and remains an indispensable tool for nanostructuring
facilities.
Once the pattern is defined and developed, the residue is rinsed off to provide the
mask. The exposed facet of the sample material can then for instance be etched or
metallised. Different etching techniques result in different structuring qualities, as
can be seen for the examples of micropillar etchings based on wet-chemical etching,
plasma or reactive-ion etching discussed for instance in [20, 21]. It should be noted
that etching rates can be different for different materials and crystal orientations,
and that the aspect ratio, shape and amount of underetching strongly depend on the
combination of etch, sample and exposure time. The interested reader is referred to
textbooks on processing techniques, e.g. [22].
More straight forward is the metallisation process of a masked sample. Either a
patterned resist is used, which is lifted off after metal deposition (e.g. by physical
vapour deposition or sputtering), or by a shadow mask, which is placed on top of
the sample and exposes the desired sample region to the deposition of metal. In both
cases, removal of the mask leaves behind the metallised areas and the previouslyprotected non-metallised surfaces.
For high-precision contacting schemes, typically lithography steps are involved,
which require homogeneous plane deposition of (polymer) resist material, development of the resist, setting free of facets for metallisation, and rinsing of the residues
after the whole process. Indeed, this is the preferred method for device fabrication
with high-precision contacts, and widely used for 2D-materials optoelectronic device
preparation.
In (nowadays rather rare) situations, where no micron or sub-micron precision
is needed, coarse masking with a shadow mask remains an option. A shadow mask
can be produced for instance by laser cutting from a ten-micrometer thin sheet of
aluminium foil. In [23], such shadow mask has been used to deposit a sequence of
20 nm titanium and 200 nm gold as films on top of each other to form electric contacts
on graphene, to give an example (see Fig. 7.3). However, with this approach, electrode
gaps on the order of 30 to 40 nm pose a lower limit.