16 Processing and Reliability of Solder Interconnections …
495
16.3.1.2 Consumer Electronics
Maximum temperature excursions are typically in the range of 0–55 °C [24]. The
ramp rates are relatively slow so that consumer electronics rarely encounter conditions that would be categorized as thermal shock (T > 20 °C/min). Exposure time
durations can be relatively long, on the order of several hours. Therefore, temperature
cycling is, intrinsically, of a lesser concern for stacked package interconnections in
consumer products.
By-and-large, consumer products that contain stacked packages are not exposed
to significant vibration conditions.
Probably the most critical environment encountered by consumer electronics
is the mechanical shock of a device being dropped to a hard surface—so-called
“drop shock” resistance. Electronic assemblies can experience accelerations of 400–
4000 Gs [24]. The resulting forces peak, and then diminish, in time frames of 1–5 ms.
For example, a study described in Ref. [15] used a drop “tower” measuring 1.4 m in
height. In spite of the relatively short distance, the impact acceleration was measured
at 3700 Gs and duration of 0.4 ms. The extent of damage expected from the impact
depends strongly upon the orientation of the assembly with respect to the falling direction. Lastly, land transportation (truck or train) and handling (loading/unloading) can
introduce shock conditions on consumer electronics. However, these loads are typically of lesser magnitudes than those caused by dropping the product on to a hard
surface.
Because the results of the drop test are strongly dependent upon the test parameters, a specification has been developed to standardize such test procedures JEDEC
Standard No. 22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products (JEDEC, Arlington, VA 2003). Several stacked packages
are soldered to the PCB test vehicle. The test vehicles are dropped multiple times.
Failures, which are typically electrical opens in a daisy chain loop, are recorded by
the test equipment. The failure data are reported in the 2P Weibull distribution format
as percent of packages failed as a function of number of drops. The characteristic
lifetime, which is the number of drops required to reach a failure of 63.2% of the
sample population, provides a measure of the solder joint reliability.
The drop test is important to guide design decision with respect to using stacked
packages. For example, the study in Ref. [14] concluded that placing underfill in
both gaps of a PoP component improved drop shock performance versus those units
receiving underfill only in the bottom gap. M. Drieiza, and co-workers examined the
drop test survivability of a PoP component by separating failures of the first-level
interconnections from those of the second-level interconnections [25]. The important
findings of this work were: (1) the solder alloy composition has a significant effect
on board level reliability and (2) package bending moments are responsible for a
majority of the solder joint failures.
Stacked packages are more prone to failure under shock loads than are most other
surface mount devices. First of all, PoP and PoPoP components have relatively high
profiles, which introduces bending moments into the interconnections. In particular,
these bending moments cause peel loads at the solder joints, a loading mode in
495
16.3.1.2 Consumer Electronics
Maximum temperature excursions are typically in the range of 0–55 °C [24]. The
ramp rates are relatively slow so that consumer electronics rarely encounter conditions that would be categorized as thermal shock (T > 20 °C/min). Exposure time
durations can be relatively long, on the order of several hours. Therefore, temperature
cycling is, intrinsically, of a lesser concern for stacked package interconnections in
consumer products.
By-and-large, consumer products that contain stacked packages are not exposed
to significant vibration conditions.
Probably the most critical environment encountered by consumer electronics
is the mechanical shock of a device being dropped to a hard surface—so-called
“drop shock” resistance. Electronic assemblies can experience accelerations of 400–
4000 Gs [24]. The resulting forces peak, and then diminish, in time frames of 1–5 ms.
For example, a study described in Ref. [15] used a drop “tower” measuring 1.4 m in
height. In spite of the relatively short distance, the impact acceleration was measured
at 3700 Gs and duration of 0.4 ms. The extent of damage expected from the impact
depends strongly upon the orientation of the assembly with respect to the falling direction. Lastly, land transportation (truck or train) and handling (loading/unloading) can
introduce shock conditions on consumer electronics. However, these loads are typically of lesser magnitudes than those caused by dropping the product on to a hard
surface.
Because the results of the drop test are strongly dependent upon the test parameters, a specification has been developed to standardize such test procedures JEDEC
Standard No. 22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products (JEDEC, Arlington, VA 2003). Several stacked packages
are soldered to the PCB test vehicle. The test vehicles are dropped multiple times.
Failures, which are typically electrical opens in a daisy chain loop, are recorded by
the test equipment. The failure data are reported in the 2P Weibull distribution format
as percent of packages failed as a function of number of drops. The characteristic
lifetime, which is the number of drops required to reach a failure of 63.2% of the
sample population, provides a measure of the solder joint reliability.
The drop test is important to guide design decision with respect to using stacked
packages. For example, the study in Ref. [14] concluded that placing underfill in
both gaps of a PoP component improved drop shock performance versus those units
receiving underfill only in the bottom gap. M. Drieiza, and co-workers examined the
drop test survivability of a PoP component by separating failures of the first-level
interconnections from those of the second-level interconnections [25]. The important
findings of this work were: (1) the solder alloy composition has a significant effect
on board level reliability and (2) package bending moments are responsible for a
majority of the solder joint failures.
Stacked packages are more prone to failure under shock loads than are most other
surface mount devices. First of all, PoP and PoPoP components have relatively high
profiles, which introduces bending moments into the interconnections. In particular,
these bending moments cause peel loads at the solder joints, a loading mode in